Address Inversion Control for Semiconductor Memory Testing
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Solution Overview
Problem
The creation of test programs for semiconductor memories that can switch between bit inverted and non-bit inverted addresses is difficult due to the need for advanced consideration of address inversion, leading to increased power consumption and complexity in testing.
Innovation Solution
A test apparatus comprising an address generator, a selector for bit inversion, an inversion processing section, and a supply section that manages an inversion cycle signal to control whether bit inversion occurs, allowing for reduced power consumption by minimizing bit logic changes during address processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If bit inversion is performed on addresses to reduce power consumption, then power consumption is reduced, but test program creation becomes difficult and troublesome
Solution Approach 1:
The memory device automatically performs bit inversion on addresses based on the inversion cycle signal without requiring external control. This self-service mechanism eliminates the need for complex test program creation while achieving power consumption reduction through dynamic address inversion.
2Use of energy by moving object
If the memory switches between bit inverted and non-bit inverted addresses, then power consumption is reduced, but the complexity of address processing increases
Solution Approach 1:
The memory device periodically alternates between bit inverted and non-bit inverted address modes using an inversion cycle signal. This periodic switching reduces average power consumption by minimizing bit transitions while the automatic inversion mechanism keeps address processing complexity manageable.
Solution Approach 2:
The memory device dynamically changes the inversion parameter of addresses based on the inversion cycle signal. By altering whether bit inversion is applied or not, the system optimizes power consumption without requiring complex additional processing circuitry.
3Measurement precision
If test programs are created with advanced consideration of address inversion, then testing accuracy is improved, but test program creation time increases
Solution Approach 1:
The memory device autonomously manages address inversion based on the inversion cycle signal, eliminating the need for test programmers to manually consider inversion details. This self-service approach maintains testing accuracy while dramatically reducing test program creation time and complexity.
Data Source
AI summary
Provided is a test apparatus including: an address generator that generates an address of a memory under test; a selector that selects whether to perform bit inversion on the address generated by the address generator before supplying the address to the memory under test; an inversion processing section that outputs the address generated by the address generator after performing bit inversion on the address if the selector has selected in the affirmative, and outputs the address generated by the address generator without performing any bit inversion on the address if the selector has selected in the negative; and a supply section that supplies, to the memory under test, the address having undergone inversion control outputted from the inversion processing section and an inversion cycle signal that indicates whether the address outputted from the inversion processing section is bit inverted or not.