Address Line Wiring Structure for Memory Signal Integrity
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Solution Overview
Problem
In high-speed memory systems, the stub structure for address signal wiring leads to waveform distortion, rising waveform blunting, and jitter due to negative reflections at branch points, which can cause signal reading errors and synchronization failures.
Innovation Solution
The address line wiring structure is designed with specific wiring lengths between branch points to cancel out negative reflected waves, ensuring that positive reflected waves reach memory elements after the threshold voltage has been exceeded, thereby preventing waveform distortion and delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a stub structure with branch points is used for memory signal wiring, then signal distribution to multiple memory elements is achieved, but characteristic impedance decreases causing waveform distortion and jitter
Solution Approach 1:
The patent changes the physical parameter of wiring length to control signal reflection timing. By setting TL0 ≥ TL1 and TL3 > TL0, TL1, the patent adjusts propagation delays to achieve destructive interference of reflected waves at critical moments, thereby maintaining signal integrity while using a stub structure for distribution.
Solution Approach 2:
The patent converts the harmful effect of signal reflections at branch points into a beneficial effect by carefully designing wiring lengths so that reflected waves arrive at memory elements after the threshold voltage has been exceeded, thus preventing waveform distortion and jitter while still using the stub structure for signal distribution.
2Speed
If signal transmission speed is increased for high-speed memory, then data processing performance improves, but waveform distortion and jitter become more severe
Solution Approach 1:
The patent changes the wiring length parameters to scale with signal speed. By setting TL0 ≥ TL1 and TL3 > TL0, TL1, the patent ensures that reflection cancellation remains effective even at higher transmission speeds, allowing performance improvement without sacrificing signal reading accuracy.
Solution Approach 2:
The patent applies preliminary anti-action by pre-calculating and setting wiring lengths to prevent waveform distortion before it occurs. The design ensures that reflected waves are timed to arrive after threshold crossing, proactively preventing the harmful effects that would otherwise worsen with increased signal speed.
3Quantity of substance
If multiple branch points are used to connect multiple memory elements, then memory capacity increases, but reflected waves interfere in complicated manner causing jitter
Solution Approach 1:
The patent changes the wiring length parameters for each branch to control reflection timing. By setting TL0 ≥ TL1 and TL3 > TL0, TL1, the patent coordinates the arrival times of reflected waves from multiple branch points, preventing complicated interference patterns and jitter while supporting multiple memory elements for increased capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces waveform distortion and delay, allowing for accurate signal transmission and improved performance in high-speed memory systems by carefully managing the wiring lengths between branch points.
Implementation Method 1
negative reflection in transmitted waves, causing waveform distortion or blunting in a rising waveform
Implementation Method 2
reflected waves mutually interfere in a complicated manner at the branch points, inducing an oscillating jitter in a signal waveform
Data Source
AI summary
An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.