Address Mapping Table Compression via Logical Address Set Segmentation
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Solution Overview
Problem
The existing data storage devices using semiconductor memory devices face challenges in efficiently managing address mapping tables, leading to large resource requirements and inefficiencies in address conversion processes.
Innovation Solution
A method is introduced to construct address mapping tables by compressing logical addresses into sets with a start logical address and valid address flags, reducing the size of the table and optimizing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a traditional address mapping table is used to map all logical addresses to physical addresses, then complete address conversion capability is achieved, but the table size becomes large consuming excessive memory resources
Solution Approach 1:
The patent segments the address mapping table by organizing logical addresses into sets grouped by their most significant bits. Instead of mapping every individual logical address, the system creates entries for address sets where addresses sharing the same high-order bits map to the same physical address range. This segmentation reduces the number of table entries while maintaining effective address conversion for all logical addresses.
Solution Approach 2:
The patent extracts and utilizes only the necessary high-order bits of logical addresses for creating mapping table entries. By taking out the least significant bits that vary within address sets, the system reduces the information needed for mapping while still achieving complete address conversion capability through the extracted high-order bit patterns.
2Measurement precision
If the address mapping table is made larger to include all logical addresses, then address conversion accuracy is improved, but memory resource consumption increases
Solution Approach 1:
The patent applies segmentation by dividing the full address space into sets based on common high-order bits. This allows the system to maintain precise address conversion for all logical addresses while using far fewer table entries, as multiple logical addresses sharing the same high-order bits are represented by a single table entry pointing to the same physical address range.
3Productivity
If individual logical addresses are mapped one-by-one, then complete address mapping is achieved, but the address conversion process becomes time-consuming
Solution Approach 1:
The patent segments address mapping into set-based entries where multiple logical addresses are grouped together and mapped to a single physical address range. During address conversion, the system can quickly determine which set a logical address belongs to and retrieve the corresponding physical address without processing individual addresses one-by-one, significantly improving conversion speed.
Solution Approach 2:
The patent implements preliminary action by pre-organizing logical addresses into sets with their corresponding physical address mappings during system initialization or idle periods. This pre-computed set-based mapping structure is then ready for rapid query during actual data operations, avoiding the need to perform address conversion calculations in real-time for each individual address.
Data Source
AI summary
A data storage device includes a nonvolatile memory device, and a controller configured to construct logical address sets each including a start logical address and valid address flags corresponding to the start logical address, from logical addresses provided from a host device, generate an address mapping table by mapping each of the logical address sets to a physical address of the nonvolatile memory device, and perform a request from the host device, by referring to the address mapping table.