Address Mapping With Mixed Translation Units to Reduce Write Amplification

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Solution Overview

Problem

Existing memory sub-systems face challenges in managing large non-volatile memory devices due to the rapid increase in the size of volatile memory needed for logical-to-physical mapping information, leading to increased write amplification and reduced reliability of non-volatile memory devices, especially in types like QLC memory.

Innovation Solution

Implementing an address mapping table that uses mixed translation unit sizes based on the number of input/output chunks, selecting smaller units for smaller requests and larger units for larger requests to reduce the number of entries in the logical-to-physical mapping table, thereby reducing unnecessary write amplification and volatile memory requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a single large translation unit size is used for all memory requests, then the number of mapping table entries is reduced, but write amplification increases for small requests

Engineering Contradiction:
Improvenumber of mapping table entriesVSAvoidwrite amplification
Core Design Contradiction:
Quantity of substanceVSLoss of energy

Solution Approach 1:

The translation unit size is segmented into multiple levels (e.g., 4KB, 16KB, 64KB) based on the size of the memory request. Small requests use smaller translation units while large requests use larger translation units, allowing the system to optimize between mapping table size and write amplification for different request patterns.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The translation unit size is made dynamic rather than fixed, allowing it to adapt based on the request characteristics. The system selects appropriate translation unit sizes from multiple available sizes according to the number of I/O chunks in each request, enabling flexible optimization of both mapping table entries and write amplification.

Inventive Principle:
Principle #15Dynamics

2Quantity of substance

If a single large translation unit size is used, then volatile memory requirements are reduced, but non-volatile memory reliability decreases due to unnecessary write operations

Engineering Contradiction:
Improvevolatile memory sizeVSAvoidnon-volatile memory reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

Multiple translation unit sizes are segmented and assigned based on request characteristics, preventing unnecessary writes to non-volatile memory while keeping volatile memory requirements manageable through efficient mapping table organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The translation unit size parameter is changed dynamically based on the number of I/O chunks in each request. This parameter adaptation allows the system to minimize write operations to non-volatile memory by selecting appropriate translation unit sizes, thereby improving reliability while maintaining acceptable volatile memory usage.

Inventive Principle:
Principle #35Parameter changes

3Loss of energy

If smaller translation unit sizes are used for all requests, then write amplification is reduced, but the number of mapping table entries and volatile memory requirements increase

Engineering Contradiction:
Improvewrite amplificationVSAvoidvolatile memory size
Core Design Contradiction:
Loss of energyVSQuantity of substance

Solution Approach 1:

The translation unit size is made dynamic, selecting from multiple sizes (4KB, 16KB, 64KB) based on the request size. This dynamic selection reduces mapping table entries for large requests while maintaining small translation units for small requests, optimizing both write amplification and volatile memory usage.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The translation unit size parameter is adjusted based on the number of I/O chunks in each request. This parameter change strategy allows the system to use smaller translation units when needed to reduce write amplification while using larger translation units when appropriate to minimize mapping table size and volatile memory requirements.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250217282A1Address mapping table for a memory sub-system using mixed translation unit sizes
Publication Date: 2025.07.03 MICRON TECHNOLOGY INC
  • US20250217282A1 patent drawing
  • US20250217282A1 patent drawing
  • US20250217282A1 patent drawing

AI summary

A processing device in a memory sub-system receives a plurality of requests to write data to a non-volatile memory device, the plurality of requests comprising respective numbers of input/output (I/O) chunks of a fixed size, and performs a plurality of write operations to write the data to the non-volatile memory device using respective translation units, wherein the respective translation units comprise two or more different translation unit sizes selected based on the respective numbers of I/O chunks of the plurality of requests.