Address Path Circuit Row Redundancy Detector Relocation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional address path circuits with a row redundant scheme in semiconductor devices require a detector in each bank, increasing chip area and hindering speed improvement due to the need for fuse circuits in each core area.
Innovation Solution
The detector is relocated to a peri-area, allowing for reduced chip area and improved operating speed by installing it outside each bank, with a configuration including an address buffer, command buffer, pre-latch unit, detector, address latch unit, and global address generator to differentiate between normal and repaired addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a detector is installed in each bank of the core area to detect whether an address is normal or repaired, then the detection function is achieved, but the chip area increases and operating speed deteriorates
Solution Approach 1:
The patent merges the detector from multiple banks into a single shared detector located in the peri-area. Instead of having separate detectors in each bank, one detector is shared across all banks to perform address detection, thereby reducing the total chip area while maintaining the detection function.
Solution Approach 2:
The single detector in the peri-area serves multiple banks simultaneously, making it a universal component that performs the same detection function for all banks. This multi-functional approach eliminates the need for dedicated detectors in each bank.
2Reliability
If a detector with fuse circuits is installed in each bank, then repaired address detection is enabled, but the operating speed is hindered due to the time required for detection
Solution Approach 1:
The detector is positioned in the peri-area to perform address detection earlier in the signal path, before the address is distributed to individual banks. This preliminary detection allows the system to determine whether an address is normal or repaired before bank-specific operations begin, improving overall operating speed.
3Adaptability or versatility
If detectors are distributed in each bank, then local address detection is possible, but the device complexity and chip area increase
Solution Approach 1:
The detection function is extracted from the individual banks and consolidated into a separate detector unit in the peri-area. This extraction simplifies the bank structure by removing detectors from each bank while maintaining the detection capability through the centralized unit.
Data Source
AI summary
An address path circuit with a row redundant scheme may include an address buffer for buffering an external address to output an internal address, a command buffer for buffering a plurality of external commands, a pre-latch unit for pre-latching the internal address from the address buffer using a specific one of the commands buffered by the command buffer to output a pre-latched internal address, a detector for detecting whether the pre-latched internal address from the pre-latch unit is a repaired address or normal address and outputting one or more detection signals as a result of the detection, an address latch unit for latching the internal address from the address buffer synchronously with a buffered clock to output a latched internal address, and a global address generator for receiving the detection signals from the detector and the latched internal address from the address latch unit and generating a global row address.