Address Protection Circuit for Memory Data Integrity
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Solution Overview
Problem
Existing memory interfaces face challenges in protecting and verifying address data, as corruption of address data can lead to incorrect data being written or read from memory devices, which is particularly critical in applications like automobiles and space exploration where reliability is paramount.
Innovation Solution
A circuit and method that generate an address protection value based on the write address, expanding the address range and incorporating it into the data bus, allowing for verification of address data by comparing the generated protection value with the value stored in memory, ensuring accurate data placement and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address data is transmitted over input/output lines without protection, then device complexity is reduced, but reliability deteriorates due to potential corruption from single event upsets
Solution Approach 1:
An address protection circuit is introduced as an intermediary component between the address bus and memory device. This circuit generates an address protection value based on the address data and transmits it through the data bus, allowing verification at the memory device without fundamentally altering the address bus structure.
Solution Approach 2:
The address protection value is generated in advance before memory access operations. The protection circuit computes the protection value based on the address data, and this pre-computed value is then transmitted along with the data to be written, enabling verification before the actual memory access occurs.
2Reliability
If address protection values are generated and transmitted through the data bus, then reliability of address data improves, but the width of the data bus must increase
Solution Approach 1:
The address protection value is merged with the data to be written into a single composite data stream on the data bus. Instead of requiring a separate dedicated bus for address protection, the system combines address protection information with existing data transactions, utilizing the same physical bus infrastructure.
Solution Approach 2:
The data bus is made multi-functional by using it to carry both regular data transactions and address protection values. The same physical bus infrastructure serves dual purposes: transmitting user data and transmitting protection information for verification, eliminating the need for additional dedicated address protection buses.
3Reliability
If protection mechanisms are implemented for data signals, then data integrity is improved, but the ability to detect address corruption deteriorates because data at incorrect addresses may not be corrupted
Solution Approach 1:
The protection mechanism is segmented into separate components: address protection value generation, address protection value transmission, and address verification. By separating address protection from data protection, the system can specifically target and detect address corruption without being confounded by data integrity checks.
Solution Approach 2:
A verification mechanism provides feedback by comparing the received address protection value with a newly generated protection value from the received address. If they match, the address is verified as correct; if they differ, address corruption is detected. This feedback loop enables specific detection of address errors that would otherwise go unnoticed.
Data Source
AI summary
A circuit is for protecting memory address data. The circuit may include an input data bus configured to receive write data to be written to a memory device, and an address bus configured to receive a corresponding write address. The circuit may also include an output data bus, and an address protection circuit coupled to the input data, address, and output data buses and configured to generate an address protection value based on the corresponding write address, and generate modified write data, on the output data bus. The modified write data includes the write data and the address protection value. The output data bus may have a width greater than a width of the input data bus.