Physical Address Proxy Reuse in Load/Store Queue Coherency
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Solution Overview
Problem
Cache memories in microprocessors impact performance due to access time and cache coherency issues, affecting processor efficiency and capacity, particularly in multi-processor systems.
Innovation Solution
Implementing a microprocessor with a first-level cache, a second-level set-associative cache, and a load/store queue that uses physical address proxies (PAPs) to manage cache coherency, including removal and filling of cache entries while preventing concurrent use of proxies, thereby optimizing cache performance and size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cache memory capacity is increased to improve hit rate, then processor performance is improved, but physical size and area of the cache increases
Solution Approach 1:
The cache is divided into multiple levels (L1, L2, L3) with different capacities and access speeds. The L1 cache provides fast access for frequently used data, while the L2 and L3 caches provide larger capacity for less frequently accessed data, resolving the contradiction between speed and capacity
Solution Approach 2:
The cache hierarchy is structured as nested levels where L1 is contained within the overall cache system, L2 contains L1's less frequently accessed data, and L3 contains L2's less frequently accessed data. This nested structure allows the system to achieve large effective capacity while maintaining fast access times for critical data
2Loss of time
If cache memory access time is reduced to improve processor cycle time, then processor performance is improved, but cache capacity must be reduced
Solution Approach 1:
Different parts of the cache hierarchy are optimized for different qualities: L1 cache is optimized for fast access time with smaller capacity, while L2 and L3 caches are optimized for larger capacity with slightly slower access times. This local optimization resolves the contradiction by ensuring that the most critical data is accessed fastest while still providing large overall capacity
3Productivity
If amount of metadata (tags, status, replacement information) is reduced to increase cache capacity, then cache hit rate is improved, but cache coherency management becomes more difficult
Solution Approach 1:
Physical address proxies act as intermediaries between the cache data structures and the coherency management system. The proxies contain minimal metadata (valid bit and physical address) that enables both cache operation and coherency management without requiring extensive tag information, resolving the contradiction between simplicity and manageability
4Productivity
If physical address proxies are reused after cache line removal to optimize proxy usage, then proxy utilization is improved, but risk of using proxies for incorrect addresses increases
Solution Approach 1:
Before reusing a physical address proxy for a new cache line, the system performs a preliminary snoop check to verify that the proxy is not currently being used by any load/store queue entries. This preliminary verification ensures safe reuse while maintaining high utilization, resolving the contradiction between optimization and reliability
Data Source
AI summary
Each load/store queue entry holds a load/store physical address proxy (PAP) for use as a proxy for a load/store physical memory line address (PMLA). The load/store PAP comprises a set index and a way that uniquely identifies an L2 cache entry holding a memory line at the load/store PMLA when an L1 cache provides the load/store PAP during the load/store instruction execution. The microprocessor removes a line at a removal PMLA from an L2 entry, forms a removal PAP as a proxy for the removal PMLA that comprises a set index and a way, snoops the load/store queue with the removal PAP to determine whether the removal PAP is being used as a proxy for the removal PMLA, fills the removed entry with a line at a fill PMLA, and prevents the removal PAP from being used as a proxy for the removal PMLA and the fill PMLA concurrently.