Address Range Expander for 32-bit Processor Memory Access
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Solution Overview
Problem
Modern computing applications using low-power system-on-chip (SOC) architectures with 32-bit processors are limited by their 32-bit address space, restricting them from utilizing larger address ranges of physical memory devices, leading to sub-optimal performance and requiring costly and complex redesigns to accommodate larger memory devices.
Innovation Solution
The implementation of address range expanders that transform processor addresses using expansion parameter registers, allowing processors to access larger memory ranges without modifying internal processor subcomponents, enabling the use of larger memory devices with 36-bit or 40-bit address spaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the processor's internal subcomponents (caches and memory management unit) are modified to support a larger address range, then the processor can utilize larger memory devices, but the design complexity and cost increase significantly
Solution Approach 1:
An address expander circuit is introduced as an intermediary component between the processor and the memory device. This circuit receives the processor's native address bus signals and expands them to the larger address space required by the memory device, allowing the processor to access larger memory without modifying its internal subcomponents. The address expander acts as a mediator that translates between the processor's address space and the memory device's address space.
2Adaptability or versatility
If the processor's internal subcomponents are redesigned to support a larger address range, then larger memory devices can be utilized, but the area available for other SOC components on the chip is reduced
Solution Approach 1:
The address expansion functionality is extracted from the processor's internal subcomponents and placed in a separate address expander circuit. This extraction allows the processor's internal caches and memory management unit to remain unchanged and retain their original area requirements, while the address expander circuit handles the address space expansion externally. This separation preserves chip area for other SOC components.
3Adaptability or versatility
If a different processor with a larger address range is chosen, then larger memory devices can be utilized, but cost and power constraints are violated
Solution Approach 1:
The address expander circuit provides multi-functionality by enabling a standard, cost-effective processor to access various memory device sizes through address expansion. Rather than requiring different processors for different memory capacities, the same processor paired with an address expander can universally support multiple memory configurations, reducing manufacturing costs and maintaining compatibility with existing processor designs.
Data Source
AI summary
An address range expander associated with a processor and a physical memory device determines that address transformation has been enabled with respect to an address indicated on the processor's address bus. The expander generates, using one or more address expansion parameter registers, a transformed address corresponding to the untransformed address within an address range of the physical memory device, and transmits the transformed address to a controller of the physical memory device.