System Address Reconstruction Logic for Memory Controllers
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Solution Overview
Problem
Existing memory systems face challenges in reliably reconstructing the original system address from a channel address due to bit discarding during system to channel address translation, especially when dealing with varying configurations of memory controllers and data transfer granularities, which limits error identification and reporting capabilities.
Innovation Solution
The implementation of system address reconstruction logic that calculates and compares bits from the channel address to reconstruct the original system address fields, accommodating different configurations of memory controllers and data transfer granularities, and includes calculator, comparator, and generator logic to generate intermediate binary address fields and concatenate them to form a reconstructed system address.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is interleaved across multiple memory controllers and channels to increase transfer speed, then productivity is improved, but loss of information occurs as address bits are discarded during translation
Solution Approach 1:
The patent applies preliminary action by calculating and storing the relationship between system address bits and channel address bits in advance through translation lookup tables (TLBs). The TLBs pre-compute and store mapping relationships between full system addresses and truncated channel addresses, enabling the system to recover original address information without losing bits during actual data transfer operations.
Solution Approach 2:
The patent uses translation lookup tables (TLBs) as an intermediary structure between the channel address and the original system address. The TLBs store intermediate mapping information that bridges the gap between the truncated channel address and the complete system address, allowing reconstruction of the original address without directly preserving all original bits during the interleaved transfer process.
2Device complexity
If address bits are discarded during system to channel address translation to simplify addressing, then device complexity is reduced, but reliability of address reconstruction deteriorates
Solution Approach 1:
The system performs preliminary calculation and storage of address mapping relationships in TLBs before actual data transfer. By pre-computing the mapping between system addresses and channel addresses, the system maintains reliability of address reconstruction while keeping the actual transfer mechanism simple and avoiding complex real-time calculations.
Solution Approach 2:
The patent creates a copy of the address mapping relationship in the translation lookup tables. Instead of attempting to directly recover the original system address from the truncated channel address, the system copies and stores the complete mapping information in advance, allowing reliable reconstruction by looking up the stored copy of the original address mapping.
3Productivity
If multiple memory controllers with parallel data paths are used to increase transfer throughput, then productivity is improved, but difficulty of detecting and measuring original address information increases
Solution Approach 1:
The translation lookup tables serve as an intermediary that bridges the parallel data paths and the original address space. Each memory controller's TLB stores the mapping relationship specific to its channel, allowing the system to detect and measure the original address information by looking up the stored mapping rather than attempting to directly track address information through multiple parallel paths.
Solution Approach 2:
The patent segments the address translation function by implementing separate translation lookup tables in each memory controller. This segmentation allows each controller to independently manage its own address mapping, making it easier to detect and measure original address information within each segment rather than attempting to track addresses across the entire parallel system as a whole.
Data Source
AI summary
System address reconstruction logic in accordance with one embodiment of the present description, reconstructs a system address from a channel address translated from the system address. The system address reconstruction logic includes logic configured to reconstruct one or more systems address fields as a function of the channel address, the number of memory controller target ways of the memory being equal to three, the number of bits of the granularity of interleaving of data among the memory controller target ways, the number of channels per memory controller target way, and the number of bits of the granularity of interleaving of data among the channels of a memory controller target way. Other aspects are described herein.