Address Remapping Circuit for Stacked Memory Devices
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Solution Overview
Problem
Current memory systems face challenges in optimizing the real memory structure to maximize performance due to simplified address management schemes, which can limit the ability to adapt to increasing memory capacity and operation speed demands.
Innovation Solution
A stacked memory device with an address remapping circuit that receives chip selection and identification signals, generates internal chip selection signals based on a remapping control signal, and selectively accesses semiconductor dies to optimize address management, allowing for adaptive operation modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simplified address management scheme is used in the memory controller, then the design complexity is reduced and operation speed is improved, but the ability to optimize the real memory structure is limited
Solution Approach 1:
An address remapping circuit is introduced as an intermediary component between the memory controller and the stacked memory devices. This circuit receives chip selection signals and chip identification signals from the memory controller, processes them through logic circuits, and generates remapped chip selection signals that properly address the three-dimensional memory structure. This intermediary solution allows the simplified memory controller to effectively manage the complex stacked memory architecture without requiring complex address management logic in the controller itself.
Solution Approach 2:
The address remapping function is segmented into distinct logical components: input signal reception, chip selection signal processing, chip identification signal processing, and remapped signal generation. This segmentation allows each component to be optimized independently while maintaining overall system simplicity.
2Adaptability or versatility
If multiple chip selection signals and chip identification signals are received, then the ability to select specific semiconductor dies is improved, but the number of input terminals and circuit complexity increases
Solution Approach 1:
The address remapping circuit merges the processing of chip selection signals and chip identification signals into a unified logic structure. Both types of signals are processed through complementary logic circuits that work together to generate the final remapped chip selection signal, reducing the need for separate processing paths and minimizing overall circuit complexity.
Solution Approach 2:
The address remapping circuit is designed with universal input terminals that can receive different combinations of chip selection signals and chip identification signals depending on the interface mode. The same circuit structure can adapt to various signaling schemes, making it multi-functional without requiring separate dedicated circuits for each signal type.
3Adaptability or versatility
If the address remapping circuit is included in all semiconductor dies, then the selection flexibility is improved, but the manufacturing complexity and cost increase
Solution Approach 1:
The address remapping functionality is merged into a single component - the master semiconductor die - rather than being distributed across all dies. The master die contains the complete address remapping circuit that processes all chip selection and chip identification signals, while slave dies simply receive the remapped signals without requiring their own remapping logic. This consolidation significantly simplifies manufacturing while maintaining full address remapping capability.
Data Source
AI summary
A memory system includes an address remapping circuit and a first set of memory devices. The address remapping circuit includes a plurality of input terminals for receiving a plurality of chip selection signals and a plurality of chip identification signals. The address remapping circuit receives input signals corresponding to a portion of the plurality of chip selection signals and the plurality of chip identification signals through corresponding input terminals of the plurality of input terminals and generates a plurality of internal chip selection signals based on the input signals and a remapping control signal. Each of the first set of memory devices is configured to be selected in response to a corresponding internal chip selection signal of the plurality of internal chip selection signals.