Address Remapping Unit Parallel Processing DMA Translation

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

In computer systems, the performance of address remapping and cache searching is hindered by the limitations of existing I/O virtualization technologies, which struggle to efficiently translate virtual addresses to physical addresses, particularly in scenarios involving direct memory access (DMA) requests, leading to reduced data processing speed and increased latency.

Innovation Solution

The implementation of an address remapping unit with four parallel processing units that decode and process DMA remapping requests by translating virtual addresses to physical addresses, utilizing a cache-control logic unit for efficient cache searches and a two-step translation method involving context and IOTLB caches, along with a page-structure cache to enhance remapping efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If existing I/O virtualization technologies are used for address remapping, then I/O device functionality is maintained, but address remapping performance and cache search speed are insufficient

Engineering Contradiction:

Improveaddress remapping performanceVSAvoiddata processing speed

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The address remapping unit is divided into multiple parallel processing units (first processing unit, second processing unit, third processing unit, fourth processing unit), each capable of independently decoding and processing remapping requests. This segmentation allows concurrent processing of multiple DMA remapping requests, significantly improving address remapping performance and reducing data processing latency.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a two-step translation method involving context cache and IOTLB cache, adding an intermediate translation dimension. The first processing unit translates virtual addresses to intermediate addresses using context cache, while the second processing unit completes the translation to physical addresses using IOTLB cache. This multi-dimensional translation approach improves cache hit rates and overall remapping efficiency.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If DMA remapping requests are processed sequentially, then processing complexity is reduced, but data processing speed decreases

Engineering Contradiction:

Improvedata processing speedVSAvoidprocessing unit structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The processing unit is segmented into four independent parallel units, each handling DMA remapping requests concurrently. The first processing unit decodes requests and translates virtual addresses to intermediate addresses, while the second processing unit completes the translation to physical addresses. The third and fourth processing units handle additional remapping operations, enabling parallel processing that significantly increases data processing speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first processing unit performs preliminary address translation by converting virtual addresses to intermediate addresses before the second processing unit completes the translation to physical addresses. This preliminary action allows the second processing unit to work on different requests simultaneously, improving overall processing throughput without requiring complex coordination between sequential units.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If cache search is performed using traditional methods, then cache structure is simple, but cache miss rate increases

Engineering Contradiction:

Improvecache hit rateVSAvoidcache control logic

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a two-step cache translation process: first using context cache to translate virtual addresses to intermediate addresses, then using IOTLB cache to complete the translation to physical addresses. This two-dimensional cache structure increases the cache hit rate by providing multiple translation stages, reducing the likelihood of cache misses compared to traditional single-stage cache systems.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The context cache acts as an intermediary between the virtual address space and the physical address space, translating virtual addresses to intermediate addresses. The IOTLB cache then serves as a second intermediary layer that completes the translation to physical addresses. This intermediary cache structure improves hit rates by capturing intermediate translation results, reducing the need to search through the entire address space.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12072813B2Method for remapping virtual address to physical address and address remapping unit

Publication Date: 2024.08.27 VIA ALLIANCE SEMICON CO LTD

AI summary

A method for remapping a virtual address to a physical address is provided. The method is used in an address remapping unit and includes: receiving, by a remapping processing unit of the address remapping unit, a remapping request, decoding the remapping request and determining whether the remapping request has a direct memory access (DMA) remapping request; and executing, by the remapping processing unit, a remapping procedure: translating a virtual address corresponding to the remapping request to a physical address, when the remapping request has the DMA remapping request.