Address Reordering for Efficient Prefetch Training
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Solution Overview
Problem
Existing computing systems face challenges in achieving improved processing performance while reducing power consumption, as prefetching mechanisms are costly in terms of memory cycles and power consumption, and prior solutions have not effectively addressed these issues.
Innovation Solution
The proposed solution involves an apparatus and method that includes an instruction dispatch module and an address reordering module, which filters program instructions and allocates tags and virtual addresses to enable efficient prefetching by filtering out repeated cache-line accesses and reconstructing virtual addresses in program order, allowing the prefetch module to train on unique cache-line accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If prefetching is used to improve processing performance, then processing performance is improved, but power consumption and memory cycle cost increase
Solution Approach 1:
The patent applies partial action by selectively filtering only certain program instructions for prefetching based on cache hit/miss status. Instead of prefetching all memory accesses, the system identifies and filters instructions that are cache hits, sending only cache misses to the prefetch module. This reduces unnecessary prefetch operations and associated power consumption while maintaining performance benefits for actual memory needs.
Solution Approach 2:
The patent segments the program instruction stream into different categories based on cache access patterns. By dividing instructions into those that are cache hits versus cache misses, the system can apply different handling strategies - filtering out hits from prefetch and processing misses through prefetch. This segmentation enables more efficient resource utilization and reduces wasted prefetch operations.
2Productivity
If prefetching is used to improve processing performance, then processing performance is improved, but memory cycle cost increases
Solution Approach 1:
The system performs partial prefetching by filtering program instructions based on cache status before sending to the prefetch module. This selective approach reduces the number of memory cycles consumed by prefetch operations while maintaining the performance benefits for actual memory needs, thereby reducing memory cycle cost.
Solution Approach 2:
The patent implements preliminary filtering of program instructions before they reach the prefetch module. By checking cache hit/miss status in advance and filtering out redundant prefetch candidates, the system prepares only necessary instructions for prefetching, reducing unnecessary memory cycle consumption and improving overall efficiency.
3Productivity
If address reordering is implemented to enable efficient prefetching, then prefetching efficiency is improved, but device complexity increases
Solution Approach 1:
The patent introduces an address reordering module as an intermediary component between the instruction dispatch module and the prefetch module. This module acts as a mediator that filters and reorders program instructions based on cache status, enabling efficient prefetching without requiring complex modifications to the existing processor architecture. The intermediary handles the complexity of address reordering and filtering in a dedicated, manageable component.
Data Source
AI summary
A computing system includes: an instruction dispatch module module configured to receive a program instruction; and an address reordering module, coupled to the instruction dispatch module, configured to filter the program instruction when the program instruction is a hit in a cache-line in a prefetch filter. The computer system further includes: an instruction dispatch module configured to receive a program instruction; an address reordering module, coupled to the instruction dispatch module, configured to: allocate a tag in a tag module for the program instruction in a program order, allocate a virtual address in a virtual address module for the program instruction and out-of-order relative to the program order, and insert a pointer associated with the tag to link the tag to the virtual address.