Address Scrambling Circuit for Flash Memory Data Transmission
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Solution Overview
Problem
Conventional memory scrambling methods are inefficient and difficult to maintain when applied to flash memory with a serial interface, leading to low data transmission efficiency.
Innovation Solution
A memory access apparatus and method featuring an address scrambling circuit that interprets original access addresses into regional unit indexes and generates scrambled unit indexes using a random address generation algorithm, ensuring that when higher-level unit indexes are the same, the scrambled indexes are identical, thus maintaining address continuity for efficient memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory scrambling method is used, then memory content protection is achieved, but data transmission efficiency deteriorates and data maintenance becomes difficult
Solution Approach 1:
The address is segmented into multiple parts: original access address, regional unit level, and unit index. The scrambling operation is applied selectively to specific segments (unit index) rather than the entire address, enabling efficient maintenance operations while preserving security.
Solution Approach 2:
Different parts of the address are treated differently: the regional unit level remains unchanged for maintenance efficiency, while only the unit index portion is scrambled for security. This local differentiation resolves the contradiction between protection and efficiency.
2Reliability
If conventional memory scrambling method is used, then memory content protection is achieved, but data maintenance difficulty increases
Solution Approach 1:
By segmenting the address into regional unit level and unit index, the invention enables maintenance operations to work with unscrambled regional unit levels, making data maintenance straightforward while unit index scrambling provides security.
Solution Approach 2:
The address scrambling circuit acts as an intermediary that translates between original access addresses and scrambled addresses. For maintenance operations, the circuit can work with the original address structure, simplifying maintenance while still providing scrambled protection for data access.
3Reliability
If random address generation algorithm is used for scrambling, then address security is improved, but address continuity deteriorates
Solution Approach 1:
The scrambling is applied locally to the unit index portion of the address while keeping the regional unit level unchanged. This localized approach provides security through scrambling while preserving address continuity at the regional level for efficient maintenance operations.
Solution Approach 2:
The address scrambling circuit dynamically adjusts the scrambling operation based on the regional unit level. When the same regional unit level is accessed, the circuit generates consistent scrambled addresses, maintaining continuity while still providing security through the scrambling transformation.
Data Source
AI summary
The present invention discloses a memory access apparatus having address scrambling mechanism that includes an address scrambling circuit and a memory controller. The address scrambling circuit performs the steps outlined below. An original access address is received to be interpreted into original unit indexes and a minimal original unit according to regional unit levels of a memory. Scrambled unit indexes and a minimal scrambled unit are generated correspondingly according to a random address generation algorithm, to further generate a scrambled access address accordingly, in which when a plurality of different original access addresses have at least one the same original unit indexes from the highest block unit level, the scrambled unit indexes generated therefrom are the same. The memory controller accesses the memory according to the scrambled access address.