Address Selection Circuit for Row Hammer Refresh in Memory
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Solution Overview
Problem
The reduction in physical volume of memory bits in semiconductor storage technologies leads to reduced charge storage and increased data loss probability, necessitating a timely refresh operation to suppress the row hammer effect and maintain storage performance and reliability.
Innovation Solution
An address selection circuit comprising an address receiving circuit, a row hammer address generation circuit, and a decoding circuit, which generates a target address and actual active address signals to automatically identify and repair redundancy addresses, thereby refreshing row hammer addresses and improving memory performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the physical volume of memory bit is reduced to increase storage density, then storage capacity is improved, but charge storage capability deteriorates and data loss probability increases
Solution Approach 1:
The patent performs preliminary identification of row hammer addresses and preliminary refresh operations before actual data loss occurs. The address selection circuit proactively identifies addresses susceptible to row hammer effects and refreshes them in advance, preventing charge loss and data errors before they happen.
Solution Approach 2:
The patent implements a feedback mechanism where the address selection circuit continuously monitors and identifies row hammer addresses, determines their refresh needs, and executes refresh operations based on this feedback. The system uses feedback from address identification to dynamically control the refresh process, ensuring charges are replenished before data loss occurs.
2Reliability
If timely refresh operation is performed on row hammer addresses to suppress row hammer effect, then data reliability is improved, but device complexity increases due to need for address selection circuit
Solution Approach 1:
The address selection circuit performs multiple functions: it identifies regular refresh addresses, identifies row hammer addresses, determines refresh needs, and controls refresh operations. By consolidating these multiple functions into a single circuit, the patent reduces overall system complexity compared to having separate circuits for each function.
Solution Approach 2:
The patent merges the address identification function and the refresh control function into a single integrated address selection circuit. This combination eliminates the need for separate identification and control circuits, reducing device complexity while maintaining the ability to perform timely refresh operations on row hammer addresses.
3Productivity
If automatic identification and repair of redundancy addresses is implemented, then storage performance is improved, but manufacturing complexity increases
Solution Approach 1:
The address selection circuit automatically identifies row hammer addresses and determines their refresh needs without external intervention. The circuit self-manages the refresh process by selecting appropriate addresses and controlling refresh operations, eliminating the need for complex external control mechanisms and simplifying manufacturing.
Data Source
AI summary
Embodiments of the present disclosure relate to an address selection circuit and a control method thereof, and a memory. The address selection circuit includes an address receiving circuit, a row hammer address generation circuit, and a decoding circuit. The address receiving circuit is configured to output a first address output signal in response to a first selection signal, where the first address output signal includes a received regular refresh address signal or an active address signal. The row hammer address generation circuit is configured to: generate a second address output signal and a row hammer address redundancy identifier according to the first selection signal, an actual active address signal, and the first address output signal. The decoding circuit is configured to: generate a target address and the actual active address signal according to the second address output signal and the row hammer address redundancy identifier.