Address Shift Circuit for Continuous DSP Memory Access
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Solution Overview
Problem
Existing digital signal processors face challenges in optimizing memory accesses, limiting performance improvement despite various coding methods, due to the large number of repetitive operations and memory accesses required for digital signal processing tasks.
Innovation Solution
A continuous memory access acceleration circuit incorporating a register circuit, arithmetic circuit, and address shift circuit, which includes a counter, counting control circuit, and adder circuit, automatically shifts memory addresses through hardware, omitting the need for explicit memory address calculation instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital signal processing is implemented with traditional memory access methods, then the processor can perform basic operations, but the performance is limited due to the large number of repetitive memory access instructions required
Solution Approach 1:
The patent pre-calculates and stores address offsets in an offset storage unit before they are needed. The address offset is computed based on the data address and stride value, and this pre-computed offset is then used to quickly generate subsequent memory addresses without repeating the full calculation, thus reducing memory access time and improving processing speed
Solution Approach 2:
The patent introduces an address acceleration circuit as an intermediary component between the processor and memory. This circuit includes an offset storage unit, adder unit, and multiplexer that work together to automatically generate memory addresses using the formula: new_address = data_address + offset. This intermediary handles the repetitive address generation task, freeing the processor from executing numerous memory access instructions and significantly improving processing throughput
2Productivity
If coding methods are optimized to reduce instruction count, then some performance improvement may be achieved, but memory access optimization remains difficult and performance is still limited
Solution Approach 1:
The address acceleration circuit operates autonomously to generate memory addresses without requiring complex processor instructions. It automatically retrieves the data address, fetches the pre-stored offset, performs the addition via the adder unit, and outputs the new address through the multiplexer. This self-service mechanism simplifies the overall system by handling address generation independently, reducing the complexity of memory access control while improving processing efficiency
Data Source
AI summary
A continuous memory access acceleration circuit, an address shift circuit, and an address generation method are provided. An arithmetic circuit calculates a memory access address according to temporary data provided by a register circuit. A counter provides a count value. A counting control circuit controls the counter to accumulate the count value according to access times of a memory. An adder circuit adds the memory access address and the count value to generate a target memory access address.