Address-Sliced Processor Cache for Lower Memory Ordering Latency
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Solution Overview
Problem
Existing processor architectures face challenges in efficiently managing memory operations due to complex ordering and coherence checks, particularly when memory instructions access addresses in an unbalanced pattern, leading to inefficiencies in latency and bandwidth utilization.
Innovation Solution
The memory circuitry is divided into clusters and slices based on address values, with L0 MEM handling common loads in parallel with L1 MEM, and L1 MEM being sliced by address to reduce ordering checks and improve scalability, using crossbar switches for transitions between domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory is divided into slices based on address values, then ordering checks are reduced and scalability is improved, but device complexity increases
Solution Approach 1:
The memory system is divided into multiple slices (e.g., slice 0, slice 1, slice 2, slice 3) based on address value ranges. Each slice independently handles memory operations for its assigned address range, eliminating the need for global ordering checks across the entire memory space. This segmentation directly reduces ordering check complexity while maintaining overall system functionality.
Solution Approach 2:
Each memory slice is assigned specific address ranges (e.g., slice 0 handles addresses 0x0000-0x0FFF, slice 1 handles 0x1000-0x1FFF, etc.). This local specialization allows each slice to operate independently with optimized local ordering checks, improving overall memory operation efficiency while distributing the complexity across multiple simpler units rather than one complex centralized memory.
2Loss of time
If L0 MEM handles common loads in parallel with L1 MEM, then latency is reduced, but device complexity increases
Solution Approach 1:
L0 MEM is positioned as a first-level cache that pre-handles common load operations before requests reach L1 MEM. By anticipating and processing frequent access patterns at the L0 level, the system reduces latency for common operations while maintaining a simplified L1 MEM structure that only handles less frequent or more complex operations.
Solution Approach 2:
L0 MEM acts as an intermediary layer between the processor and L1 MEM. It intercepts and handles common load operations, allowing L1 MEM to focus on more complex or less frequent operations. This intermediary structure reduces the overall latency by handling simple cases quickly while maintaining the benefits of the larger L1 MEM capacity.
Data Source
AI summary
Techniques for slicing memory of a hardware processor core by linear address are described. In certain examples, a hardware processor core includes memory circuitry having: a cache comprising a plurality of slices of memory, wherein each of a plurality of cache lines of memory are only stored in a single slice, and each slice stores a different range of address values compared to any other slice, wherein each of the plurality of slices of memory comprises: an incomplete load buffer to store a load address from the address generation circuit for a load request operation, broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, in response to the load address being within a range of address values of that memory slice, a store address buffer to store a store address from the address generation circuit for a store request operation, broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, in response to the store address being within a range of address values of that memory slice, a store data buffer to store data, including the data for the store request operation that is to be stored at the store address, for each store request operation broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, and a store completion buffer to store the data for the store request operation in response to the store address being stored in the store address buffer of that memory slice, and, in response, clear the store address for the store request operation from the store address buffer and clear the data for the store request operation from the store data buffer.