Two-Level Address Space Access Control for Memory Efficiency
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Solution Overview
Problem
In data processing systems with large address spaces and limited memory, managing access control efficiently is challenging, especially when multiple masters access the address space, as it requires significant memory resources and can increase latency.
Innovation Solution
Implementing a two-level access system with coarse grain access circuitry to provide references to areas of the address space and fine grain access circuits to further refine these references, reducing the number of entries needed and minimizing memory usage by eliminating invalid entries and allowing for granular access control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large address space is provided to support multiple masters with different access permissions, then system compatibility and access control capability are improved, but memory consumption increases significantly
Solution Approach 1:
The address space is divided into multiple address ranges, with each range managed by a separate address range register. This segmentation allows the system to cover a large address space without storing permission information for the entire space, thereby reducing memory consumption while maintaining comprehensive address space support.
Solution Approach 2:
Different address ranges are assigned to different masters with specific access permissions. Each address range register stores permission information localized to its specific range, allowing fine-grained access control for each master without requiring global permission tables, thus reducing overall memory usage.
2Quantity of substance
If memory management is moved into software to reduce hardware memory usage, then hardware resource consumption is reduced, but access latency increases significantly
Solution Approach 1:
Address range registers are pre-configured with address ranges and access permissions before runtime operations. This preliminary configuration allows the system to perform fast hardware-based access control checks during runtime without requiring software intervention, thereby reducing access latency while minimizing hardware memory usage.
Solution Approach 2:
The address range registers act as an intermediary hardware structure that bridges the gap between full hardware memory management and software-based management. They provide a compact hardware representation of address space partitions, enabling fast access control without the overhead of full software memory management, thus balancing memory usage and latency.
3Measurement precision
If detailed access control information is stored for all address space combinations, then access control precision is improved, but memory requirements increase
Solution Approach 1:
The address space is segmented into multiple address ranges, each managed by a dedicated address range register. This segmentation enables precise access control within each range while avoiding the need to store permission information for every possible address combination, thereby maintaining high access control granularity with reduced memory requirements.
Solution Approach 2:
Instead of storing complete permission information for all address space combinations, the system stores only the essential address range boundaries and associated permissions. This partial action approach provides sufficient access control precision for practical purposes while significantly reducing memory requirements compared to storing full permission matrices.
Data Source
AI summary
There is provided an apparatus for receiving a request from a master to access an input address. Coarse grain access circuitry stores and provides a reference to an area of an output address space in dependence on the input address. One or more fine grain access circuits, each store and provide a reference to a sub-area in the area of the output address space in dependence on the input address. The apparatus forwards the request from the coarse grain access circuitry to one of the one fine grain access circuits in dependence on the input address.