Stream-Specific Address Compression for Redundant Bus Traffic
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Solution Overview
Problem
Current address compression technologies, such as dynamic base register caching and stride address compression, do not achieve a high enough compression ratio due to the inefficiencies in transferring address information, leading to waste of bandwidth and limited system memory capacity.
Innovation Solution
The method involves determining a compression algorithm based on the address features of operation request messages with the same stream number, compressing consecutive addresses with the same attribute information, and constructing message packets with both compressed and uncompressed information parts to improve the address compression ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If complete address is transferred without using locality features, then address information is fully transmitted, but redundant information is transferred causing waste of bandwidth and power consumption
Solution Approach 1:
The patent extracts only the necessary address information by separating addresses into high-order parts and low-order parts, transferring only the high-order part through the inter-processor bus while the low-order part is generated locally at the receiving end, thereby eliminating redundant information transfer and reducing power consumption
Solution Approach 2:
The patent segments the address into multiple parts (high-order part and low-order part) that can be handled differently - the high-order part is transferred between processors while the low-order part is generated locally, optimizing the balance between information completeness and transmission efficiency
2Loss of information
If complete address is transferred without using locality features, then address information is fully transmitted, but physical bandwidth is wasted
Solution Approach 1:
The patent extracts only the essential high-order address part for transmission, removing redundant low-order parts that can be regenerated locally, thereby improving bandwidth utilization while maintaining address information completeness
Solution Approach 2:
The address is segmented into high-order and low-order parts, with only the high-order part transmitted across the bus, optimizing bandwidth usage by transmitting minimal necessary information
3Length of stationary object
If 32-bit address limit is applied, then transfer width is constrained, but system memory capacity is limited to 4G
Solution Approach 1:
The patent extends the address space by adding a high-order part that is transferred between processors, effectively moving from a 32-bit address space to a larger address space (e.g., 48-bit or more), thereby enabling system memory capacity to exceed the 4G limitation while maintaining compatibility with existing 32-bit architectures
4Loss of energy
If dynamic base register caching is used, then temporal locality is exploited, but compression ratio is insufficient
Solution Approach 1:
The patent segments the address into high-order and low-order parts, transferring only the high-order part, which significantly improves compression ratio compared to traditional base register caching that transfers more address information
Solution Approach 2:
The patent introduces a new dimension of address handling by separating and differently treating high-order and low-order parts, enabling more aggressive compression while maintaining address translation functionality
5Loss of energy
If stride address compression is used, then spatial locality is exploited, but compression ratio is insufficient
Solution Approach 1:
The patent segments the address into high-order and low-order parts, transferring only the high-order part, achieving superior compression ratio compared to stride address compression that operates on complete addresses
Solution Approach 2:
The patent extracts and transfers only the high-order address part, removing redundant low-order information that can be regenerated locally, thereby achieving higher compression ratio while maintaining spatial locality benefits
Data Source
AI summary
An address compression method, an address decompression method, a compressor, and a decompressor are disclosed, wherein the address compression method includes after a compressor receives multiple operation request messages that are sent by a first processor, determining, according to an address feature formed by address information carried in all operation request messages that have a same stream number, a compression algorithm corresponding to the operation request messages that have a same stream number; and then compressing, according to the determined compression algorithm, addresses carried in the operation request messages that have a same stream number. The present invention is applicable to the computer field.