Address Swizzling for 3D Stacked Memory Thermal Management
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Solution Overview
Problem
Thermal issues in 3D stacked memory devices limit memory capacity and performance due to heat dissipation challenges, as processor cores generate heat during operation, leading to increased power consumption and degradation of memory performance.
Innovation Solution
Address swizzling is employed in processing systems with stacked memory, where a single memory address is swizzled to access different physical locations on multiple memory dies, distributing heat generation and reducing hotspotting by alternating access patterns between memory banks or quadrants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D stacked memory is used to increase memory capacity and bandwidth, then memory capacity and communication between stacked dies are improved, but thermal issues and heat dissipation challenges worsen
Solution Approach 1:
The memory address space is segmented and mapped to different physical locations across multiple stacked memory dies. By dividing the access pattern into separate spatial segments, the patent distributes heat generation across multiple dies rather than concentrating it in a single location, thereby improving thermal management while maintaining increased memory capacity through vertical stacking.
Solution Approach 2:
The patent introduces a dimensional transformation in address mapping, where linear address sequences are mapped to two-dimensional or three-dimensional physical layouts across stacked dies. This dimensional change allows access patterns that naturally distribute thermal load across the vertical stack, resolving the contradiction between increased capacity and heat dissipation challenges.
2Productivity
If multiple threads access stacked memory in parallel to increase bandwidth, then communication efficiency is improved, but thermal hotspots and localized heat generation worsen
Solution Approach 1:
The patent applies local quality by assigning different access patterns to different threads based on their spatial distribution. Each thread is configured to access specific regions of the stacked memory, creating localized access patterns that prevent concurrent threads from generating heat at the same physical location. This maintains high bandwidth through parallel access while distributing thermal hotspots across different regions.
Solution Approach 2:
The address mapping scheme introduces asymmetry in how different threads access memory locations. By using asymmetric address-to-physical-location mappings, the patent ensures that parallel threads access different physical regions, distributing thermal load asymmetrically across the stack rather than creating symmetric hotspots, thereby maintaining productivity while reducing thermal concentration.
3Power
If processor cores operate at high performance, then compute capability is improved, but power consumption and heat generation worsen
Solution Approach 1:
The patent converts the harmful effect of concentrated heat generation into a beneficial distributed access pattern. By designing the address mapping to naturally spread out access patterns, the system transforms what would be concentrated thermal hotspots into distributed thermal patterns, allowing high-performance compute operations while improving thermal management and reducing localized power density issues.
Data Source
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AI summary
A processing system [100] includes a compute die [102] and a stacked memory [104] stacked with the compute die. The stacked memory includes a first memory die [104B] and a second memory die [104A] stacked on top of the first memory die. A parallel access using a single memory address is directed towards different memory banks [206, 208] of the first memory die and the second memory die. The single memory address of the parallel access is swizzled to access the first memory die and the second memory die at different physical locations.