Address Token Ring Topology for Page Collision Prevention
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Solution Overview
Problem
Complex computing systems with multiple processing units accessing shared memory experience performance degradation due to page collisions, which increase latency and reduce throughput, especially when the number of access streams exceeds the number of memory banks.
Innovation Solution
A communication scheme is implemented where multiple components share memory access requests through a ring topology, passing an address token to avoid page collisions by ensuring sequential addresses are used for memory access, allowing multiple memory regions to be accessed concurrently without closing previously opened pages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple DMA engines independently write to shared memory, then data transfer throughput is improved, but page collisions increase causing latency to worsen
Solution Approach 1:
An address token is introduced as an intermediary that circulates among DMA engines in a ring topology. The token carries address information and grants permission for memory access, coordinating multiple DMA engines to avoid simultaneous access to the same memory page, thereby preventing page collisions while maintaining high throughput
Solution Approach 2:
The address token is updated in advance with the next sequential memory address before being passed to the next DMA engine. This preliminary action ensures that when a DMA engine receives the token, it already has the correct address information needed for the next memory access, eliminating the need to close and reopen pages
2Productivity
If the number of access streams exceeds the number of memory banks, then concurrency is improved, but page collision probability increases
Solution Approach 1:
The address token acts as a mediator that serializes access requests from multiple DMA engines. Even though multiple streams can initiate requests concurrently, the token ensures that only one DMA engine accesses a particular memory page at a time, preventing collisions while allowing high stream concurrency
Solution Approach 2:
The system changes the address parameter sequentially as the token circulates through the ring topology. Each DMA engine receives an updated address from the token, ensuring that consecutive accesses target different memory pages even when multiple streams are active, thereby eliminating page collisions
Data Source
AI summary
To generate sequential addresses when multiple integrated circuit (IC) devices are accessing the same memory, an address token is sent along the IC devices communicatively coupled in a ring topology. The address token is first transferred along the ring topology during a memory reservation phase in which each IC device can set a corresponding memory request bit to indicate that the IC device has data to write to the memory. The modified address token is then transferred along the ring topology again during a memory access phase. During the memory access phase, each IC device that has data to write can perform a memory write operation using a sequential address determined from the contents of the address token.