Address Translation Circuit for Multi-Bank Memory Error Correction
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Solution Overview
Problem
Existing memory systems face challenges in accurately detecting and correcting errors due to mismatches between detected error-related addresses and actual addresses, particularly when multiple memory bank groups are tested simultaneously, leading to incomplete detection data.
Innovation Solution
An address translation circuit that includes a frequency division circuit and an address counter, which adjusts the frequency of address increment signals and introduces a jump signal to manage address counting across multiple memory bank groups, ensuring accurate address translation and error correction in both X8 and X16 modes without requiring large-scale circuit modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple memory bank groups are tested simultaneously to reduce space occupied by detection and error correction circuits, then the detection and error correction capability is improved, but the accuracy of error-related addresses matching with actual addresses deteriorates, leading to incomplete detection data
Solution Approach 1:
The patent introduces an address translation circuit as an intermediary component between the error detection circuit and the memory bank groups. This circuit includes a frequency division circuit that divides the address increment signal frequency by N (where N is the number of memory bank groups), and an address counter that counts addresses for each bank group. The address translation circuit translates the global address into bank-group-specific addresses, enabling accurate address matching while allowing simultaneous testing of multiple bank groups.
Solution Approach 2:
The patent segments the address counting function by introducing separate address counters for each memory bank group. Each counter independently counts addresses within its respective bank group, while the frequency division circuit coordinates the counting across all bank groups. This segmentation allows each bank group to be tested with accurate address tracking while maintaining the ability to test multiple groups simultaneously.
2Productivity
If the address counter counts addresses at a high frequency to improve detection speed, then the productivity is improved, but the complexity of managing address translation across multiple memory bank groups increases
Solution Approach 1:
The patent implements continuous address counting across all memory bank groups using the frequency division circuit. The circuit continuously divides the address increment signal by N and feeds it to the address counters, ensuring that address translation is maintained throughout the entire detection process without interruption. This continuous operation enables high-speed detection while keeping the address translation mechanism simple and coordinated.
Solution Approach 2:
The frequency division circuit serves as an intermediary that simplifies the coordination between high-speed address counting and multi-bank-group translation. By dividing the frequency by N, it automatically synchronizes the counting across all bank groups, reducing the complexity of managing address translation while maintaining high detection speed.
Data Source
AI summary
A address translation circuit includes: a frequency division circuit, configured to receive a first address increment signal with a first frequency, process the first address increment signal, and output a second address increment signal with a second frequency as well as a jump signal with the second frequency, where the jump signal is used to indicate a first address jumping among the N memory banks; an address counter, configured to receive the second address increment signal and output an address count signal; and a row address increment circuit, configured to output a first row address increment signal when the address count signal indicates that column address counting has been finished, and the jump signal indicates a last memory bank group.