Address Translation Cache Coalescing via Prefetch Circuitry
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Solution Overview
Problem
Existing address translation cache technologies face inefficiencies in utilizing resources due to limited flexibility in page aggregation, leading to increased latency in handling requests, as they are constrained by the number of descriptors that can be fetched during a page table walk.
Innovation Solution
An apparatus with an address translation cache and prefetch circuitry that detects contiguous access conditions to retrieve descriptors from a page table, producing coalesced address translation data for multiple virtual pages and allocating it into the cache, allowing for flexible and efficient coalesced data storage without impacting live request handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If hardware page aggregation is performed to overcome software technique limitations, then address translation cache utilization is improved, but request handling latency increases
Solution Approach 1:
The system performs preliminary actions by detecting contiguous access patterns and pre-fetching descriptors from the page table before they are actually needed. The prefetch circuitry proactively retrieves descriptors and produces coalesced address translation data in advance, so that when a request arrives, the data is already ready in the address translation cache, eliminating the latency penalty of on-demand aggregation.
Solution Approach 2:
The invention segments the address translation process into distinct phases: detection of contiguous access conditions, selective prefetching of descriptors, production of coalesced data, and allocation to cache entries. This segmentation allows the system to apply hardware aggregation only when beneficial (contiguous accesses) while maintaining fast paths for non-contiguous accesses, thus improving overall cache utilization without universally increasing latency.
2Productivity
If coalesced address translation data is allocated into cache entries, then resource utilization is improved, but complexity of allocation process increases
Solution Approach 1:
The allocation process is made dynamic through the detection of contiguous access conditions. The system adaptively decides whether to perform coalesced allocation or standard allocation based on runtime access patterns. When contiguous accesses are detected, coalesced data is allocated to multiple cache entries simultaneously; otherwise, standard individual allocation proceeds. This dynamic behavior improves resource utilization while keeping the complexity conditional rather than universal.
Solution Approach 2:
The prefetch circuitry acts as an intermediary between the page table and the address translation cache. It retrieves descriptors, produces coalesced address translation data, and triggers the allocation process. This intermediary layer simplifies the overall system architecture by centralizing the complex coalescing logic in a dedicated component, making the allocation process more manageable and modular.
Data Source
AI summary
An apparatus and method are provided for determining address translation data to be stored within an address translation cache. The apparatus comprises an address translation cache having a plurality of entries, where each entry stores address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. Via an interface of the apparatus, access requests are received from a request source, where each access request identifies a virtual address. Prefetch circuitry is responsive to a contiguous access condition being detected from the access requests received by the interface, to retrieve one or more descriptors from a page table, where each descriptor is associated with a virtual page, in order to produce candidate coalesced address translation data relating to multiple contiguous virtual pages. At an appropriate point, the prefetch circuitry triggers the control circuitry to allocate, into a selected entry of the address translation cache, coalesced address translation data that is derived from the candidate coalesced address translation data. Such an approach has been found to provide a particularly efficient mechanism for creating coalesced address translation data for allocating into the address translation cache, without impacting the latency of the servicing of ongoing requests from the request source.