Address Translation Cache Line Deallocation via Set-Aside Transaction
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Solution Overview
Problem
The existing memory management units (MMUs) and system memory management units (SMMUs) face performance and flexibility issues due to the presence of unneeded address translation data in translation lookaside buffers (TLBs), which impede address translation speed.
Innovation Solution
A set-aside translation transaction is introduced to indicate that a particular address translation is no longer needed, allowing the memory management unit to deallocate cache lines storing this data, thereby improving the speed and flexibility of address translation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If translation lookaside buffers (TLBs) store address translation data for multiple virtual memory addresses, then address translation speed is improved through caching, but unneeded address translation data accumulates and impedes performance and flexibility
Solution Approach 1:
The patent introduces a set-aside translation transaction that is sent in advance to indicate which address translations are no longer needed. This preliminary action allows the MMU to proactively deallocate cache lines before they would naturally be overwritten, maintaining TLB performance while improving flexibility by enabling timely eviction of unnecessary translations.
Solution Approach 2:
The set-aside translation transaction creates a feedback mechanism where the system explicitly communicates which address translations should be maintained and which should be evicted. This feedback loop allows the MMU to dynamically adjust its cache contents based on actual usage patterns, resolving the contradiction between maintaining fast translation (caching) and maintaining flexibility (eviction).
2Speed
If TLBs maintain a fixed number of cache lines for address translations, then address translation speed is maintained, but the system cannot adapt to changing translation needs
Solution Approach 1:
The patent enables dynamic management of TLB cache lines through the set-aside translation transaction mechanism. The MMU can now adaptively allocate and deallocate cache lines based on real-time translation needs, transforming the static TLB into a dynamic structure that maintains speed while improving overall system productivity through better resource utilization.
3Adaptability or versatility
If the MMU deallocates cache lines frequently to maintain flexibility, then adaptability is improved, but address translation speed decreases due to cache misses
Solution Approach 1:
By receiving set-aside translation transactions in advance, the MMU can deallocate cache lines proactively rather than reactively. This preliminary action ensures that flexibility is maintained through timely eviction of unnecessary translations, while translation speed is preserved because the MMU avoids frequent emergency evictions that would cause cache misses.
Data Source
AI summary
The present disclosure advantageously provides a memory management unit and methods for invalidating cache lines in address translation caches. The memory management unit has one or more address translation caches, and each address translation cache has a plurality of cache lines. The memory management unit receives transactions from a source of transactions. The transactions include, inter alia, memory transactions and a set-aside translation transaction. The memory transactions include at least a first memory transaction and a last memory transaction, and each memory transaction includes the same virtual memory address and the same translation context identifier. The set-aside translation transaction also includes the same virtual memory address and the same translation context identifier. In response to receiving the set-aside translation transaction, the memory management unit deallocates each cache line that stores an address translation for the same virtual memory address and the same translation context identifier.