Address Translation Cache Filter Circuitry for Splinter Condition Handling
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Solution Overview
Problem
In data processing systems with address translation caches, handling page invalidate requests becomes inefficient due to the 'splinter condition' where the first stage page size exceeds the second stage page size, leading to uncertainty about where address translation data is stored, necessitating a full cache scan, which impacts performance.
Innovation Solution
An apparatus and method that includes filter circuitry to detect the splinter condition and guide maintenance circuitry to only check specific entries of the address translation cache for page invalidate requests, reducing the need for a full cache scan by using filter entries to identify which entries need to be checked based on the presence of the splinter condition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the first stage page size exceeds the second stage page size (splinter condition), then address translation data can be obtained through multi-stage translation process, but it becomes impossible to ascertain where the relevant address translation data will have been stored within the address translation cache, requiring a full cache scan
Solution Approach 1:
The patent segments the address translation cache into multiple sets, where each set corresponds to a specific page size. When a splinter condition is detected (first stage page size exceeds second stage page size), the maintenance circuitry uses the filter circuitry to identify which specific sets contain the relevant address translation data, rather than scanning the entire cache. This segmentation allows targeted invalidation of only the necessary sets, improving performance while maintaining multi-stage translation capability.
2Reliability
If the entire address translation cache is scanned to determine entries that need to be invalidated, then all possible entries can be checked, but performance is significantly impacted
Solution Approach 1:
The patent performs preliminary action by detecting the splinter condition at the time of address translation data allocation and recording this information in the filter circuitry. When a page invalidate request arrives, the maintenance circuitry can immediately consult the filter circuitry to identify which sets need checking, rather than scanning the entire cache. This preliminary recording of splinter condition information enables fast, targeted invalidation while ensuring all relevant entries are checked.
3Device complexity
If address translation data is allocated based on the smaller of the two page sizes, then cache organization is simplified, but the splinter condition creates uncertainty about data location
Solution Approach 1:
The patent introduces the filter circuitry as an intermediary between the allocation circuitry and the maintenance circuitry. The filter circuitry records information about splinter conditions and page size mappings. When address translation data is allocated based on the smaller page size, the filter circuitry stores metadata indicating whether a splinter condition exists. The maintenance circuitry then uses this intermediary information to correctly identify which cache sets contain the relevant data, resolving the location uncertainty without changing the simple allocation scheme.
Data Source
AI summary
An apparatus is provided having processing circuitry for executing multiple items of supervised software under the control of a supervising element, and a set associative address translation cache having a plurality of entries, where each entry stores address translation data used when converting a virtual address into a corresponding physical address of a memory system comprising multiple pages. The address translation data is obtained by a multi-stage address translation process comprising a first stage translation process managed by an item of supervised software and a second stage translation process managed by the supervising element. Allocation circuitry is responsive to receipt of obtained address translation data for a specified virtual address, to allocate the obtained address translation data into an entry of a selected set of the address translation cache, where the selected set is identified using a subset of bits of the specified virtual address chosen in dependence on a final page size associated with the obtained address translation data. Filter circuitry is provided having a plurality of filter entries, and is responsive to detecting that a splinter condition exists for the obtained address translation data, to indicate in a chosen filter entry that the splinter condition has been detected for the specified item of supervised software that is associated with the obtained address translation data. The splinter condition exists when a first stage page size used in the multi-stage translation process exceeds the final page size. Maintenance circuitry is then responsive to a page invalidate request associated with an item of supervised software, to reference the filter circuitry to determine which entries of the address translation cache need to be checked in order to process the page invalidate request, in dependence on whether a filter entry of the filter circuitry indicates presence of the splinter condition for that item of supervised software.