Address Translation Cache Invalidation Filter Construct

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Solution Overview

Problem

In large symmetric multi-processor (SMP) configurations, the process of invalidating address translation information across multiple processors in a network incurs increased latency, leading to performance bottlenecks due to the need for software-controlled invalidation of address translation buffer entries in each processor.

Innovation Solution

Implementing a filter construct with outgoing and incoming filter lists that identify logical partition identifications (LPIDs) to determine which processors need to process address translation invalidation instructions, allowing only relevant processors to acknowledge and process these instructions, thereby reducing unnecessary cross-processor communication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If address translation invalidation instructions are broadcast to all processors in the system, then all processors can be ensured to invalidate their cache entries, but the processing latency increases and system throughput decreases

Engineering Contradiction:

Improvecompleteness of invalidationVSAvoidinvalidation latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the invalidation process by dividing processors into groups based on outgoing filter lists. Each processor only sends invalidation instructions to specific groups rather than broadcasting to all processors, thereby reducing the number of recipients while ensuring complete invalidation within each segment.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent pre-computes and stores outgoing filter lists that identify which processor groups need to receive invalidation instructions for each LPID. This preliminary organization allows processors to quickly determine the minimal set of recipients without scanning all processors, reducing invalidation latency while maintaining reliability.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If address translation invalidation instructions are sent to all processors, then no cache entries are left valid, but the system incurs increased processing overhead and reduced throughput

Engineering Contradiction:

Improveinvalidation completenessVSAvoidsystem throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent segments the processor network into targeted groups using outgoing filter lists, allowing invalidation instructions to be sent only to relevant processor groups rather than all processors. This segmentation maintains complete invalidation reliability while reducing the total number of instruction transmissions, thereby improving system throughput.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by sending invalidation instructions only to the minimal necessary subset of processors identified by outgoing filter lists, rather than performing excessive action of broadcasting to all processors. This partial targeting achieves complete invalidation for the affected LPID while reducing overall system overhead and improving throughput.

Inventive Principle:

Principle #16Partial or excessive action

3Adaptability or versatility

If software-controlled invalidation is used for address translation buffers, then flexibility in handling different invalidation scenarios is achieved, but the processing speed decreases

Engineering Contradiction:

Improveinvalidation flexibilityVSAvoidinvalidation processing speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent introduces outgoing filter lists as an intermediary data structure that bridges software flexibility and hardware speed. The filter lists are software-computed to provide adaptability for different invalidation scenarios, but once computed, they enable hardware-efficient targeted broadcasting that significantly improves processing speed compared to pure software-controlled invalidation.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11301392B2Address translation cache invalidation in a microprocessor

Publication Date: 2022.04.12 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.