Address Translation Storage Invalidation via Counter Segmentation
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Solution Overview
Problem
The complexity of invalidating address translation mappings in data processing systems, particularly when multiple stages of address translation are involved, leads to increased latency and performance impact due to the need to manage different addressing schemes and varying region sizes, making existing methods inefficient.
Innovation Solution
The use of address translation circuitry with counter circuitry to store and manage merged address translation information across multiple addressing schemes, allowing for efficient invalidation of entries by modifying counter values based on invalidation contexts and performing validity checks to determine entry validity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple separate address translation storage devices are used for different translation stages, then the system can maintain separate caching for each translation level, but the area occupied and the latency for separate lookups increase
Solution Approach 1:
The patent merges multiple address translation storage devices into a single unified address translation storage that caches translations across multiple stages (e.g., VA to IPA and IPA to PA) in one location. This consolidation reduces the total area occupied by address translation storage while maintaining the ability to cache translations for different translation levels, thereby resolving the contradiction between reliability and area usage.
2Ease of operation
If all TLB entries are invalidated in response to any invalidation request, then the system simplifies the invalidation process, but performance deteriorates due to serialised memory transactions and TLB misses
Solution Approach 1:
The patent segments the address translation storage into multiple independent tables (e.g., first TLB for VA to IPA translations, second TLB for IPA to PA translations). When an invalidation request occurs, only the relevant segment is invalidated rather than the entire storage. This segmentation maintains operational simplicity while preserving performance by avoiding unnecessary invalidations of unrelated translation entries.
Solution Approach 2:
The patent applies local quality by making each TLB entry valid or invalid independently based on its specific translation stage and context. Instead of a blanket invalidation approach, the system selectively invalidates only those entries that correspond to the invalidated translation mapping, thereby maintaining high productivity while keeping the invalidation process simple through localized validity changes.
3Stability of the object's composition
If the master waits for TLB invalidation to complete before continuing, then the system ensures consistency, but noticeable performance impact occurs when invalidation takes long
Solution Approach 1:
The patent implements preliminary action by pre-invalidating relevant TLB entries before the master needs to access updated translations. When a translation mapping is updated, the system proactively invalidates the corresponding cached entries in advance, so that when the master subsequently accesses the translation, the stale data is already cleared. This eliminates the need for the master to wait for invalidation completion, maintaining consistency while reducing time loss.
4Productivity
If merged address translation storage is used to cache direct virtual address to physical address mappings, then area and lookup latency are reduced, but complexity increases when invalidating entries from different translation levels
Solution Approach 1:
The patent segments the merged address translation storage into multiple independent tables, each responsible for a specific translation stage (e.g., first TLB for VA to IPA, second TLB for IPA to PA). This segmentation simplifies the invalidation process by allowing selective invalidation of only the relevant table based on the invalidation request, thereby reducing the complexity of managing merged translations while maintaining the productivity benefits of merged caching.
Solution Approach 2:
The patent introduces an intermediary mechanism (the segmented TLB structure with validity bits) that mediates between the merged address translation storage and the invalidation requests. This intermediary allows the system to maintain merged caching for high productivity while providing a simplified interface for invalidation by directing invalidation requests to the appropriate segment, thereby reducing the complexity of managing multi-level translations.
Data Source
AI summary
Apparatuses and methods for address translation invalidation are provided. In an apparatus having address translation storage which stores merged address translation information for multiple address translation stages, a set of counters are provided to hold a set of counter values. Entries in the address translation storage are stored with identifiers of first and second counters selected from the set of counters in dependence on respective context information for a first stage and a second stage of address translation together with a counter value of each counter. In response to an invalidation request specifying a first or second addressing scheme invalidation context a counter of the set of counters is selected in dependence on the first or second addressing scheme invalidation context and its value is modified. Subsequently an entry in the address translation storage is determined to be invalid when either the first counter value does not match a current value of the first counter or the second counter value does not match a current value of the second counter.