Address Translation Invalidation via Identifier Grouping

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Solution Overview

Problem

Existing address translation circuitry in data processing systems faces inefficiencies when invalidating stored address translations, particularly during context switches or when handling multiple virtual machines, as current methods often require flushing and repopulating the entire local storage, leading to performance bottlenecks.

Innovation Solution

The introduction of identifier grouping information allows for the configuration of address translation circuitry to invalidate multiple stored address translations in response to a single command by associating multiple identifiers as a group, enabling flexible and efficient invalidation of address translations based on specified addresses and identifiers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all stored address translations are flushed to ensure correct memory access permissions after a context switch, then reliability is improved, but productivity deteriorates due to the need to repopulate the entire local storage

Engineering Contradiction:
Improvememory access permissionsVSAvoidaddress translation efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts and invalidates only the specific address translation entries that are relevant to the context switch, rather than flushing the entire TLB. This is achieved by comparing the context identifier in the invalidation command with context identifiers stored in association with each address translation entry, and selectively invalidating only those matches.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the address translation invalidation process by dividing the TLB into individual entries, each associated with a context identifier. This allows targeted invalidation of specific segments (entries) rather than requiring complete invalidation of the entire structure, thereby maintaining productivity while ensuring reliability.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If a simple flush technique is used to invalidate all address translations, then ease of operation is improved, but loss of information worsens due to deletion of entire local storage content

Engineering Contradiction:
Improveinvalidation process simplicityVSAvoidstored address translations
Core Design Contradiction:
Ease of operationVSLoss of information

Solution Approach 1:

The patent extracts only the necessary address translation entries for invalidation based on context identifier matching, rather than extracting (deleting) all entries. This selective approach reduces information loss while maintaining operational simplicity through an automated matching process.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent implements a feedback mechanism where the address translation circuitry automatically compares context identifiers from invalidation commands with stored context identifiers, and selectively invalidates matching entries. This feedback-based selective invalidation reduces information loss while maintaining ease of operation through automation.

Inventive Principle:
Principle #23Feedback

3Productivity

If identifier grouping information is added to enable selective invalidation, then productivity is improved, but device complexity increases

Engineering Contradiction:
Improveinvalidation process efficiencyVSAvoidaddress translation circuitry
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the context identifier storage with the existing address translation entries in the TLB. Each TLB entry is associated with a context identifier, and the invalidation command includes a context identifier that is compared against stored identifiers. This merging approach enables selective invalidation without requiring a completely separate storage structure, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP3108372B1Invalidating stored address translations
Publication Date: 2018.07.11 ARM LTD
  • EP3108372B1 patent drawingFigure 1~2
  • EP3108372B1 patent drawingFigure 3
  • EP3108372B1 patent drawingFigure 4A~4B

AI summary

A data processing apparatus and a method of processing data are disclosed, in which address translations between first addresses used in a first addressing system and second addresses used in a second addressing system are locally stored. Each stored address translation is stored with a corresponding identifier. In response to an invalidation command to perform an invalidation process on a selected stored address translation the selected stored address translation is invalidated, wherein the selected stored address translation is identified in the invalidation command by a specified first address and a specified identifier. The invalidation process is further configured by identifier grouping information which associates more than one identifier together as a group of identifiers, and the invalidation process is applied to all stored address translations which match the specified first address and which match any identifier in the group of identifiers to which the specified identifier belongs.