Address Translation Invalidation with Return Marker for Multi-Processor Data Location

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Solution Overview

Problem

In complex computer systems, data is widely distributed, leading to increased latency when processors need to retrieve data from other processors, and it is challenging for software programmers to determine the location of data to optimize performance.

Innovation Solution

A method involving the issuance of an address translation invalidation instruction with a return marker, which is broadcast across the system to invalidate address translation entries and return information on the invalidated entries to the issuing processor, allowing for the identification of data location and improving processor performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If data is widely distributed across multiple processors, then data storage capacity and system scalability are improved, but data retrieval latency increases and performance deteriorates

Engineering Contradiction:

Improvedata storage capacityVSAvoiddata retrieval latency

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The system performs preliminary actions by broadcasting address translation invalidation instructions before actual data access occurs. This allows the system to proactively identify and cache data locations across processors, so when data is needed, it can be retrieved quickly without latency penalties.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The return marker mechanism provides feedback about data location information back to the issuing processor. This feedback loop enables the system to learn about data distribution patterns and optimize future data access operations, reducing latency while maintaining distributed storage benefits.

Inventive Principle:

Principle #23Feedback

2Adaptability or versatility

If data is widely distributed across multiple processors, then system scalability is improved, but programmer ability to optimize data retrieval deteriorates due to lack of visibility

Engineering Contradiction:

Improvesystem scalabilityVSAvoidprogrammer ability to optimize

Core Design Contradiction:

Adaptability or versatilityVSEase of operation

Solution Approach 1:

The system provides automated feedback through return markers that reveal data location information to processors. This eliminates the need for programmers to manually track data distribution, as the system automatically provides this information, maintaining ease of operation while enabling scalability.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The system performs self-service by automatically tracking and reporting data locations through the invalidation instruction mechanism. This removes the burden from programmers to manually optimize data retrieval, as the system handles data location management autonomously while remaining scalable.

Inventive Principle:

Principle #25Self-service

3Measurement precision

If address translation invalidation instructions are broadcast to all processors, then data location identification accuracy is improved, but system communication overhead increases

Engineering Contradiction:

Improvedata location identification accuracyVSAvoidsystem communication overhead

Core Design Contradiction:

Measurement precisionVSLoss of energy

Solution Approach 1:

The address translation invalidation instruction serves multiple functions: it invalidates cached translations, identifies data locations, and provides feedback through return markers. This multi-functionality reduces the need for separate communication protocols, lowering overall system communication overhead while maintaining high location identification accuracy.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10942853B2System and method including broadcasting an address translation invalidation instruction with a return marker to indentify the location of data in a computing system having mutiple processors

Publication Date: 2021.03.09 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A method, computer program product, and computer system are disclosed that in one or more embodiments includes issuing, from an issuing processor in the computer system, an address translation invalidation instruction with a return marker, wherein the address translation invalidation instruction is to invalidate one or more address translation entries in one or more storage locations in the computer system and wherein the return marker comprises an instruction to return information to the issuing processor indicating the identity of each processor where an invalidated entry was located. The method, product, and system in an embodiment further includes broadcasting the address translation invalidation instruction with the return marker to one or more storage locations of one or more of the processors in the computer system other than the issuing processor; invalidating the address translation entry corresponding to the broadcasted address translation invalidation instruction; and returning to the issuing processor information on each storage location corresponding to the invalidated address translation entry. In one or more embodiments, the returned information is used to determine the performance of the computing system, identifying the storage locations where data was located.