Address Translation Logic for Partitioned System Memory Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current partitioning techniques in information processing systems face challenges in efficiently managing guest to host address translations for devices to access memory, particularly in ensuring secure and efficient virtualization across multiple partitions without requiring software design for partitioned systems.
Innovation Solution
The implementation of address translation logic within the chipset or processor, which maps guest physical addresses to host physical addresses, allowing devices to access allocated system memory without causing a VM exit, while maintaining isolation through domain-based memory protection and translation mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If address translation logic is implemented in chipset or processor, then memory access efficiency is improved and VM exits are avoided, but device complexity increases
Solution Approach 1:
The patent introduces address translation logic as an intermediary component between devices and system memory. This intermediary translates device-generated guest physical addresses to host physical addresses, enabling efficient memory access without requiring VM exits to software. The address translation logic acts as a mediator that resolves the complexity by handling translation hardware-level, preventing software from needing to be aware of or manage the translation process.
2Reliability
If domain-based memory protection is implemented, then system security and isolation are improved, but device complexity increases
Solution Approach 1:
The patent implements domain-based memory protection by segmenting system memory into distinct domains, each associated with a specific partition. Address translation logic is configured with domain identifiers that segment the address translation process: it translates addresses within the context of a specific domain, automatically enforcing isolation between partitions. This segmentation approach improves security by ensuring devices can only access memory within their assigned domain, while the complexity is managed through hardware-level domain tagging rather than complex software policies.
3Productivity
If guest physical addresses are translated to host physical addresses without VM exit, then system performance is improved, but measurement precision of address mapping worsens
Solution Approach 1:
The patent enables address translation to occur autonomously through hardware-based address translation logic that operates independently of software intervention. When a device generates a guest physical address, the address translation logic automatically translates it to the corresponding host physical address using domain identifiers and translation tables stored in hardware. This self-service mechanism eliminates the need for VM exits, maintaining high system performance while ensuring precise address mapping through deterministic hardware translation rather than software-based approximation.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Embodiments of apparatuses, methods, and systems for guest to host address translations for devices to access memory in a partitioned system are disclosed. In one embodiment, an apparatus includes an interface, partitioning logic, first address translation logic, and second address translation logic. The interface is to receive a request from a device to access memory in a partitioned system. The partitioning logic is to determine whether the device is assigned to a first partition or a second partition. The first address translation logic is to translate a first guest address to a first host address in the first partition. The second address translation logic is to translate a second guest address to a second host address in the second partition.