Address Translation Circuitry With Page Table Size-Aware Lookups
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Solution Overview
Problem
Address translation using sequential lookups in page table levels is time-consuming, leading to latency issues.
Innovation Solution
Implement address translation circuitry that supports regular and large page table levels, performing a predetermined maximum number of lookups while suppressing additional lookups when reaching large page tables, and using intermediate lookups to generate the second address based on retrieved information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential lookups are performed in all page table levels, then complete address translation is achieved, but translation latency increases
Solution Approach 1:
The patent applies partial action by performing only the necessary number of lookups based on page table level size information. When a large page table level is detected, the circuitry suppresses additional lookups that would exceed the predetermined maximum, thereby reducing translation latency while maintaining complete address translation through intelligent lookup suppression rather than performing all possible lookups
Solution Approach 2:
The patent implements preliminary action by performing intermediate lookups to retrieve page table level size information before completing the full address translation sequence. This allows the circuitry to determine in advance how many additional lookups are needed, enabling optimized translation depth that reduces overall latency while ensuring translation completeness
2Adaptability or versatility
If large page table levels are supported with multiple entries, then address translation capacity increases, but number of lookups required increases
Solution Approach 1:
The patent applies feedback by using page table level size information retrieved during intermediate lookups to dynamically adjust the number of subsequent lookups performed. When large page table levels are detected, the circuitry receives feedback about the table size and suppresses additional lookups accordingly, maintaining high translation capacity while optimizing translation speed through adaptive lookup suppression
Solution Approach 2:
The patent implements dynamics by making the number of lookups performed dynamic rather than fixed. The circuitry adjusts the translation depth based on real-time detection of page table level sizes, allowing the system to adapt between different translation scenarios (regular vs. large page tables) to optimize both capacity and speed
3Loss of time
If predetermined maximum number of lookups is enforced, then translation time is controlled, but translation accuracy may be compromised
Solution Approach 1:
The patent ensures translation accuracy while controlling time through feedback mechanisms that monitor page table level size information during intermediate lookups. The circuitry uses this feedback to intelligently suppress additional lookups only when the predetermined maximum would be exceeded, ensuring that translation accuracy is maintained within the time constraint by suppressing lookups that would not contribute to the final translation result
Data Source
AI summary
There is provided address translation circuitry and a method for performing address translation. The address translation circuitry is responsive to receipt of a first address to perform an address translation between the first address and a second address by performing a predetermined maximum number of sequential lookups. The address translation circuitry is configured to support regular page tables comprising 2N entries and large page tables comprising 2N*M entries. The address translation circuitry is configured to: perform an intermediate lookup to retrieve information indicative of a sequentially next lookup address and page table size information and, when the page table size information indicates that the sequentially next lookup corresponds to one of the large page table and performing the sequentially next lookup would exceed the predetermined maximum number of sequential lookups, suppress subsequent lookups and generate the second address based on the information indicative of the sequentially next lookup address.