Memory Address Translation Controller for Persistent Memory Copying
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Solution Overview
Problem
The mismatch between CPU addressing scheme and persistent memory device granularity leads to increased latency during data movement, causing underutilization of memory devices and performance degradation.
Innovation Solution
A controller with a memory address decoding module translates CPU addresses into shifted addresses compatible with persistent memory granularity, distributing data across multiple devices to bridge the addressing gap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CPU addressing scheme with interleave set granularity (e.g., 4 kB) is used, then data can be stored in memory devices, but objects smaller than interleave set granularity are stored on a single memory device causing underutilization of memory devices and performance degradation
Solution Approach 1:
The patent segments the data transfer process by introducing a controller that divides the incoming data stream into smaller units matching the ECC block size granularity of persistent memory devices. This segmentation allows fine-grained data to be distributed across multiple memory devices in parallel, resolving the contradiction between maintaining CPU addressing simplicity and achieving fine-grained memory utilization.
Solution Approach 2:
The patent introduces a controller as an intermediary between the CPU and persistent memory devices. This intermediary translates CPU addresses into shifted addresses and manages the distribution of data across multiple memory devices, enabling the system to overcome the granularity mismatch without modifying the CPU addressing scheme.
2Reliability
If data is written to persistent memory with ECC block size granularity (e.g., 256 bytes), then data persistency is ensured, but the mismatch between CPU interleave set granularity and ECC block size causes increased latency
Solution Approach 1:
The patent changes the addressing parameter by introducing a shifted address scheme. The controller translates CPU addresses into shifted addresses that account for the granularity difference between CPU interleave sets and ECC blocks. This parameter transformation enables efficient mapping of fine-grained persistent memory writes to CPU addresses without compromising data persistency.
3Reliability
If memory copy operation followed by cache flush operation and memory barrier is executed, then data persistency is ensured, but the performance is bottlenecked by the single persistent memory device
Solution Approach 1:
The patent segments the data transfer across multiple persistent memory devices by distributing fine-grained data units to different devices based on shifted address mapping. This parallel distribution across multiple devices eliminates the single-device bottleneck while maintaining data persistency through proper ordering and barriers.
Solution Approach 2:
The patent adds a new dimension to the addressing space by introducing shifted addresses that map CPU addresses to a distributed memory namespace. This dimensional transformation enables parallel access across multiple memory devices while preserving the original CPU addressing simplicity and data persistency requirements.
Data Source
AI summary
A controller is provided to copy data from a processing unit to a memory system, wherein the processing unit includes a volatile memory and the memory system includes a persistent memory, wherein the controller includes a memory address decoding module that is configured to receive a first address from the processing unit, the first address is a physical address for the data to be copied to as utilized by the processing unit. The memory address decoding module is further configured to translate the first address into a second address taking into account interleaving settings and granularity of the persistent memory, wherein the second address is a shifted version of the first address, and is for the persistent memory and provide the second address to a memory controller of the memory system. The controller reduces the latency during data movement from the processing unit to the persistent memory devices.