Address Translation Metadata Compression in SSD Memory Subsystems
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high capacity requirements for volatile memory to store address translation metadata in memory devices, particularly in large capacity SSDs, lead to inefficiencies and increased access latency due to the large size of the logical-to-physical address translation table.
Innovation Solution
Implementing larger 'bundle units' for logical addresses and truncating both logical and physical addresses to reduce the size of the logical-to-physical address translation table entries, thereby reducing the overall metadata size and volatile memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large logical-to-physical address translation table is used to support high capacity memory devices, then the address translation capability is improved, but the volatile memory capacity requirement increases
Solution Approach 1:
The patent segments the address translation table into multiple smaller tables (first address translation table and second address translation table), where each table stores a portion of the address mappings. This segmentation reduces the memory capacity required in each individual table while maintaining the overall address translation capability for large capacity memory devices
Solution Approach 2:
The patent implements a nested structure where multiple address translation tables are organized hierarchically. The first address translation table maps logical addresses to intermediate physical addresses, and the second address translation table maps intermediate physical addresses to final physical addresses. This nested approach allows comprehensive address translation while using less volatile memory than a single flat table would require
2Reliability
If a large logical-to-physical address translation table is used to support high capacity memory devices, then the address translation capability is improved, but the data transfer efficiency deteriorates due to increased access latency
Solution Approach 1:
By dividing the large address translation table into multiple smaller tables, the patent enables faster access times for each individual table lookup. The segmented structure reduces the time required to search and access address mappings compared to a single large table, thereby improving data transfer efficiency while maintaining comprehensive address translation capability
Solution Approach 2:
The patent performs preliminary address translation in stages through multiple smaller tables rather than searching a single large table. This staged approach allows the system to resolve addresses more quickly by breaking down the translation process into manageable steps, reducing overall access latency
Data Source
AI summary
An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a memory access request specifying a logical address of a data item and a memory access operation to be performed with respect to the data item; produce a truncated logical address by applying a predefined mathematical transformation to the specified logical address; identifying, in an address translation table, an address translation table entry identified by the truncated logical address; and perform the memory access operation using a physical address specified by the address translation table entry.