Address Translation for Multi-Die Memory Map Compatibility
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Solution Overview
Problem
In systems-on-chip (SoC) with multiple dies, existing technologies face challenges in managing compatible memory maps, scalability of address space, and integrating dies with different address lengths, leading to inefficiencies and limitations in addressable locations and compatibility.
Innovation Solution
An interface and translator system that receives transactions with addresses from one memory space, translates them to a different memory space, and maps boot transactions to a boot region, allowing for flexible address space management and compatibility between dies with different address lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple dies share a memory space, then integration density is improved, but address space compatibility and scalability deteriorate
Solution Approach 1:
The memory space is segmented into multiple address spaces, each associated with a specific die. The address translation unit divides the address translation process into segments: first determining which address space the transaction targets, then translating the address within that specific space. This segmentation allows each die to have its own address space characteristics while enabling integration in the system package.
Solution Approach 2:
The address translation unit acts as an intermediary between the interface and the memory spaces. It receives transactions from the interface, determines the appropriate address space, performs the necessary address translation, and then routes the transaction to the correct memory space. This intermediary function resolves the compatibility issues between different die address spaces while maintaining high integration density.
2Adaptability or versatility
If dies with different address lengths are integrated, then scalability is improved, but address translation complexity increases
Solution Approach 1:
The address translation unit dynamically adapts its translation process based on the transaction type and target address space. For boot transactions, it applies specific boot address remapping logic; for other transactions, it uses standard address translation. This dynamic behavior allows the system to handle dies with different address lengths without requiring a single complex translation mechanism for all cases.
Solution Approach 2:
Different address translation rules and complexities are applied locally to different address spaces and transaction types. Boot transactions receive specialized address remapping treatment, while other transactions use standard translation. This local quality approach means that the complexity is concentrated only where needed (boot transactions and specific address spaces) rather than being uniformly distributed, reducing overall system complexity while maintaining scalability.
3Reliability
If boot transactions are mapped to a specific boot region, then booting reliability is improved, but address space flexibility is reduced
Solution Approach 1:
The boot address remapping logic is configured in advance to map boot transactions to a designated boot region in the address space. This preliminary configuration ensures that boot transactions are reliably directed to the correct region before the system begins normal operation. The boot region mapping is established as part of the address translation unit's initialization, ensuring reliable booting while allowing flexibility in the overall address space design.
Data Source
AI summary
A first arrangement including an interface configured to receive transactions with an address from a second arrangement having a first memory space; a translator configured to translate an address of a first type of received transaction to a second memory space of the first arrangement, the second memory space being different to the first memory space; and boot logic configured to map a boot transaction of the received transactions to a boot region in the second memory space.