Address Translation Circuitry for Virtual NID Memory Optimization
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Solution Overview
Problem
Current systems for configuring virtual Network Interface Devices (NIDs) in web hosting servers face challenges in optimizing system performance without increasing manufacturing costs, particularly in managing multiple virtual servers on a single physical server, and in efficiently handling PCIe address space to support virtual NID configurations.
Innovation Solution
A novel approach involving a Network Interface Device (NID) with address translation circuitry that maps PCIe addresses to smaller blocks in high-speed memory, allowing for efficient configuration and monitoring of virtual NIDs by setting programmable bits (DAT and GAA) to enable address translation and alert generation, thereby optimizing memory usage and supporting different operating systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If address translation circuitry is added to the NID to map PCIe addresses to high-speed memory blocks, then memory usage efficiency is improved and manufacturing costs are controlled, but device complexity increases
Solution Approach 1:
The patent introduces address translation circuitry as an intermediary component between the PCIe interface and the high-speed memory blocks. This circuitry translates PCIe addresses to corresponding blocks in high-speed memory, enabling efficient memory access without requiring the entire PCIe address space to be physically present in high-speed memory. The intermediary handles the mapping function, resolving the contradiction between memory efficiency and device complexity by adding only the necessary translation logic rather than duplicating entire memory structures.
Solution Approach 2:
The patent segments the large PCIe address space into multiple smaller blocks, each mapping to corresponding blocks in high-speed memory. By dividing the address space into manageable segments (e.g., 64KB blocks), the system can efficiently manage memory resources without requiring the full address space to be physically implemented in high-speed memory. This segmentation allows the NID to handle large address spaces while maintaining controlled device complexity through modular memory organization.
2Ease of manufacture
If the high-speed memory size is reduced to lower manufacturing costs, then manufacturing costs are reduced, but the ability to support all PCIe address space decreases
Solution Approach 1:
The patent resolves the contradiction between memory size and address space support by introducing a fourth dimension - address translation. Instead of increasing memory size linearly to support larger address spaces, the system uses address translation circuitry that maps the entire PCIe address space to a smaller physical memory footprint. This dimensional change allows the system to support large address spaces (e.g., 4GB PCIe space) while using much smaller high-speed memory blocks (e.g., 64KB blocks), thereby reducing manufacturing costs while maintaining full address space support.
3Adaptability or versatility
If multiple virtual NIDs are supported on a single physical NID to increase virtualization capability, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements multi-functionality by designing the address translation circuitry to handle multiple virtual NIDs simultaneously. The same physical NID hardware can service multiple virtual machines by translating PCIe addresses from different virtual NIDs to the appropriate high-speed memory blocks. The system uses virtualization-aware address translation that can dynamically route requests from multiple virtual functions to the appropriate physical resources, enabling a single physical NID to perform the work of multiple virtual NIDs without proportionally increasing device complexity.
Solution Approach 2:
The patent merges multiple virtual NID functionalities into a single physical NID hardware platform. By combining the address translation, memory management, and virtualization handling into unified circuitry, the system enables multiple virtual NIDs to share the same physical resources. This merging approach allows virtual machines to have isolated address spaces while physically sharing the NID hardware, thereby improving virtualization capability without linearly increasing device complexity through separate physical NIDs for each virtual machine.
Data Source
AI summary
A transactional memory receives a command, where the command includes an address and a novel DAT (Do Address Translation) bit. If the DAT bit is set and if the transactional memory is enabled to do address translations and if the command is for an access (read or write) of a memory of the transactional memory, then the transactional memory performs an address translation operation on the address of the command. Parameters of the address translation are programmable and are set up before the command is received. In one configuration, certain bits of the incoming address are deleted, and other bits are shifted in bit position, and a base address is ORed in, and a padding bit is added, thereby generating the translated address. The resulting translated address is then used to access the memory of the transactional memory to carry out the command.