Address Translation Using Ordered Tables
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Solution Overview
Problem
Existing address translation systems, such as memory management units (MMUs), are costly in terms of integrated circuit area due to their complexity in implementing look-up techniques like page table walks.
Innovation Solution
An ordered set of address translation tables is used, where each table provides translation data for a contiguous range of virtual memory addresses and includes location information for adjacent tables, allowing efficient navigation and reducing the need for fetching translation data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional MMUs implementing look-up techniques such as page table walks are used, then address translation functionality is achieved, but integrated circuit area cost increases
Solution Approach 1:
The patent divides the address translation system into multiple ordered address translation tables, each handling a specific contiguous range of virtual memory addresses. This segmentation allows the system to process address translations in smaller, more manageable units rather than requiring a single large MMU structure, thereby reducing the overall integrated circuit area while maintaining full address translation functionality.
Solution Approach 2:
The patent introduces an intermediary structure consisting of ordered address translation tables with location information that mediates between the virtual memory address space and physical memory addresses. This intermediary approach replaces the need for a complex traditional MMU by using a series of simpler tables that work together to achieve the same address translation function with reduced circuit area.
2Area of stationary object
If ordered address translation tables with location information are used, then integrated circuit area is reduced, but table navigation complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-organizing the address translation tables in a specific order and pre-populating them with location information about adjacent tables. This preliminary structuring is done during table creation or initialization, so that during actual address translation operations, the navigation can proceed efficiently without requiring complex real-time decision-making, thus reducing operational complexity despite the structured organization.
3Productivity
If multiple address translation tables are used, then address translation efficiency is improved, but system complexity increases
Solution Approach 1:
The patent introduces dynamics by making the address translation system adaptable to different access patterns. The ordered tables with location information allow the system to dynamically navigate through the appropriate tables based on the specific virtual memory address being translated, enabling efficient handling of both linear and non-linear access patterns while keeping the overall structure manageable through the ordered organization.
Data Source
AI summary
Address translation apparatus comprises translation circuitry to access an ordered set of two or more address translation tables stored at respective storage locations to generate an address translation between an input virtual memory address in a virtual memory address space and a respective translated memory address in a translated memory address space. Each address translation table in the ordered set of two or more address translation tables is configured to provide translation data indicating mappings between virtual memory addresses and translated memory addresses for a contiguous range of virtual memory addresses applicable to that address translation table. The ordered set of address translation tables are ordered with respect to one another according to an order of their respective ranges of virtual memory addresses for which they provide translation data. Each address translation table in the ordered set of two or more address translation tables comprises location information defining the storage location of at least those of the other address translation tables in the ordered set of two or more address translation tables which are adjacent to that address translation table in the ordered set of two or more address translation tables.