Address Translation System Using Prefetch Segments
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Solution Overview
Problem
Existing address translation systems require complex look-up functionality and significant storage space to store virtual addresses, leading to increased latency and power consumption, especially when handling large numbers of translations.
Innovation Solution
The proposed solution involves an address translation system that stores physical address information in segments, where each segment corresponds to virtual addresses in a predefined order, allowing for efficient generation of physical addresses using segment identifiers and portions of virtual addresses, and incorporates prefetch circuitry to anticipate and retrieve required segments before they are needed, reducing the need to store virtual addresses and minimizing memory access latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If virtual addresses are stored in the TLB to enable address translation, then address translation can be performed, but storage space requirements increase significantly
Solution Approach 1:
The patent extracts only the necessary physical address information from the full virtual address/physical address pairs and stores only the physical address in the TLB entry. The virtual address is not stored, but rather used as an index to retrieve the physical address from a page table in memory. This extraction of only essential data reduces storage requirements while maintaining translation capability.
Solution Approach 2:
The patent introduces a page table in memory as an intermediary structure that maps virtual addresses to physical addresses. The TLB stores references to this page table and uses segment identifiers and virtual address portions to index into the page table, rather than storing complete translation pairs. This intermediary approach reduces TLB storage needs while enabling address translation.
2Productivity
If complex look-up functionality is implemented to handle large numbers of translations, then translation capacity increases, but latency increases
Solution Approach 1:
The patent segments the address translation process into two parts: a fast TLB lookup using segment identifier and virtual address portion to directly access physical address information, and a secondary page table walk only when TLB miss occurs. This segmentation allows most translations to be resolved quickly without complex look-ups, reducing latency while maintaining high translation capacity.
Solution Approach 2:
The patent implements prefetching of physical address information from the page table into the TLB before it is actually needed. The prefetch circuitry anticipates future translation requests and loads required physical address information in advance, reducing the time needed when translations are actually requested and thereby reducing latency.
3Adaptability or versatility
If more entries are stored in the TLB to handle larger address spaces, then translation coverage increases, but power consumption increases
Solution Approach 1:
The patent extracts and stores only the physical address information in TLB entries rather than storing complete virtual address/physical address pairs. This extraction reduces the amount of data stored in the TLB, allowing the TLB to be smaller and thus consume less power while still providing comprehensive address space coverage through the page table intermediary.
Solution Approach 2:
The patent uses a partial action approach by storing only the necessary physical address information in the TLB rather than all possible translation entries. The TLB stores a subset of translations that are most likely to be accessed, with the page table providing the complete mapping on demand. This partial storage reduces power consumption while maintaining adequate address space coverage for typical workloads.
4Measurement precision
If physical address information is retrieved from memory for each translation, then translation accuracy is maintained, but retrieval time increases
Solution Approach 1:
The patent implements preliminary retrieval of physical address information from the page table and stores it in the TLB before it is actually needed for translation. The prefetch circuitry anticipates future translation requests and loads required physical address information in advance, so when a translation is requested, the information is already available in the fast TLB, eliminating the delay of retrieving from memory and reducing retrieval time while maintaining accuracy.
Solution Approach 2:
The patent segments the retrieval process into a fast TLB lookup (which provides immediate results for most cases) and a slower page table walk (which only occurs on TLB misses). This segmentation allows the system to provide accurate translations quickly for the majority of cases where the TLB has the required information, reducing average retrieval time while maintaining translation accuracy.
Data Source
AI summary
An apparatus, system, and method for address translation are provided. Physical address information corresponding to virtual addresses is prefetched and stored, where at least some sequences of the virtual addresses are in a predefined order. The physical address information is prefetched based on identification information provided by a data processing activity, comprising at least a segment identifier and a portion of a virtual address to be translated. The storage has segments of entries, wherein each segment stores physical address information which corresponds to virtual addresses in a predefined order. This predefined order means that it is not necessary to store virtual addresses in the storage. Storage capacity and response speed are therefore gained.