Logical-to-Physical Address Translation for Removable Storage

The patent introduces a lookup table as an intermediary data structure that maps logical addresses to physical addresses in NAND flash memory. This lookup table acts as a mediator between the host system and the physical memory, enabling reliable address translation without requiring complex real-time mapping algorithms. The lookup table stores pre-computed address mappings, simplifying the translation process while maintaining data reliability.

The patent performs address translation and data encryption/decryption operations in advance before data is written to or read from NAND flash memory. By pre-translating logical addresses to physical addresses and pre-encrypting data before storage, the system ensures data reliability without requiring complex operations during data access. This preliminary action approach reduces the complexity of real-time address translation while maintaining reliable data access.

The patent performs data encryption before writing to NAND flash memory and decryption before reading from it. By encrypting data in advance during the write operation and having the decryption key ready before read operations, the system ensures data security without adding significant overhead during data access. The encryption and decryption operations are integrated into the address translation process, minimizing additional access time.

The lookup table serves as an intermediary that not only maps logical to physical addresses but also stores or provides access to decryption keys. This integrated approach allows the system to retrieve both the physical address and the necessary decryption key through a single lookup operation, reducing the time penalty that would otherwise result from separate key retrieval operations.

The patent divides the address translation space into multiple lookup tables, each handling a specific range of logical addresses. Instead of creating one large lookup table that consumes excessive memory, the address space is segmented into smaller, manageable tables. This segmentation reduces the memory footprint of each individual lookup table while maintaining efficient translation performance through localized lookups.

The patent implements lookup tables with local optimization, where each lookup table is tailored to its specific address range and storage characteristics. By making the lookup table structure and size adaptive to local requirements rather than uniform across the entire address space, the system achieves high translation efficiency in each local region while minimizing overall memory usage. This local quality approach allows different parts of the address space to use appropriately sized lookup tables.