Address Translation Circuit for Storage Class Memory Wear Management

The patent introduces a memory controller as an intermediary between the processor and storage class memory. The memory controller implements wear leveling algorithms that distribute write operations across different memory blocks, preventing any single block from experiencing excessive wear. This mediator layer transparently manages the mapping between logical addresses and physical memory locations, allowing the processor to benefit from fast write performance while the memory cells are protected from premature breakdown through intelligent write distribution.

The patent extracts the wear leveling management complexity from the processor domain and places it entirely within the memory controller. The memory controller independently handles all wear leveling operations, including tracking block wear status, making decisions about data relocation, and updating address translation tables. This extraction allows the processor to access memory using simple logical addresses without needing to understand or participate in the complex wear leveling management, thereby extending memory lifespan while containing complexity within the memory controller subsystem.

The patent implements preliminary action by pre-allocating and pre-mapping memory blocks before they are fully utilized. The memory controller maintains an address translation table that is proactively updated whenever wear leveling requires data movement, rather than waiting for address conflicts to occur. This preliminary updating of address mappings ensures that wear distribution is maintained while address translations are resolved efficiently before they impact processor operations, reducing the complexity of real-time address management.