Address Translation Table Flattening for Faster Memory Access
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Solution Overview
Problem
Existing memory management systems with multiple virtual address maps face inefficiencies in accessing and caching translation tables due to the need for multiple memory accesses and the lack of effective utilization of contiguous memory regions.
Innovation Solution
The use of indicator data to indicate contiguous sets of entries in translation tables, allowing for more efficient caching and potentially omitting one or more table levels, thereby improving cache hit rates and reducing memory accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If translation tables are traversed using conventional hierarchical structures, then address translation functionality is achieved, but multiple memory accesses are required reducing system performance
Solution Approach 1:
The patent merges multiple translation table levels into a single flattened structure, allowing the MMU to access translation data in fewer memory operations. Instead of traversing hierarchical levels (L1→L2→L3), the flattened structure enables direct calculation of entry positions, reducing the number of memory accesses required and improving translation performance.
Solution Approach 2:
The patent transforms the multi-level hierarchical structure into a single-level flattened structure by changing the dimensional organization of translation data. This dimensional transformation allows the MMU to calculate entry positions directly using bit manipulation on the virtual address, eliminating the need to traverse multiple hierarchical levels and reducing memory access time.
2Ease of operation
If hierarchical translation tables are used, then comprehensive address translation is achieved, but the complexity of table traversal increases
Solution Approach 1:
The patent segments the virtual address into distinct fields (translation level select, base address, offset) that map directly to components of the flattened translation table structure. This segmentation simplifies the traversal process by allowing the MMU to independently extract and use each address component without navigating complex hierarchical relationships, reducing operational complexity while maintaining translation functionality.
3Adaptability or versatility
If multiple virtual address maps are supported, then memory management flexibility is improved, but the number of memory accesses required increases
Solution Approach 1:
The patent creates a universal flattened translation table structure that can accommodate multiple virtual address maps (different translation levels and configurations) through a unified access mechanism. The same bit manipulation and direct calculation approach works across different virtual address map configurations, providing flexibility while maintaining efficient single-level access and avoiding the need for separate traversal procedures for each map type.
Data Source
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AI summary
Apparatus comprises address processing circuitry to detect information relating to an input memory address by reference to a respective chain of information entries provided by address information tables in respective ones of an ordered plurality of hierarchical table levels; the address processing circuitry being configured to select an address information table at a given table level according to a base address dependent upon an earlier information entry in an address information table earlier than the given table level in the ordered plurality of table levels; and the address processing circuitry being configured to select an information entry in the selected address information table according to an offset component dependent upon at least a portion of the input memory address applicable to the given table level, the offset component being defined so that contiguous instances of that portion of the input memory address indicate contiguously addressed information entries; the address processing circuitry comprising detector circuitry to detect whether indicator data is set to indicate whether a group of one or more contiguously addressed information entries in the selected address information table provide at least one base address indicating a location within a contiguously addressed region comprising multiple address information tables at a later table level.