Address Translation Unit with Cryptographic Signer for Secure RDMA
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Solution Overview
Problem
In secure I/O systems, the integration of MMU in the processor I/O complex leads to shared translation cache issues, increasing space requirements and cache thrashing, and there is no effective way to ensure that translated addresses have not been tampered with, necessitating trust in vendors for correct implementation, which compromises security and performance.
Innovation Solution
An address translation unit with a signer that cryptographically signs real addresses translated from virtual addresses, reducing the need for processor-side checks and enhancing security by using client keys dynamically refreshed and managed by an external component like a smartcard, thereby reducing memory bandwidth, system cost, and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the MMU is integrated in the processor I/O complex to consolidate PCI Express and reduce system complexity, then device complexity is reduced, but the translation cache is shared between all I/O devices which increases space requirements and creates cache thrashing
Solution Approach 1:
The patent divides the translation cache into device-specific segments, where each I/O device has its own dedicated cache portion. This segmentation prevents cache thrashing by isolating translations for different devices while still using the integrated MMU architecture, thus reducing overall system complexity without increasing total cache space requirements.
Solution Approach 2:
The patent implements local quality by providing each I/O device with customized translation cache entries specific to its address translation needs. This allows the system to maintain a compact integrated MMU while ensuring each device has appropriate translation information without requiring excessive shared cache space.
2Device complexity
If the MMU is integrated in the processor I/O complex to consolidate PCI Express, then system complexity is reduced, but there is no possibility to check whether the translated address has not been changed by the I/O device, compromising security
Solution Approach 1:
The patent applies preliminary action by having the processor sign the translated address before it is returned to the I/O device. This preemptive cryptographic signing ensures the address integrity before the device can potentially modify it, maintaining security while using the simplified integrated MMU architecture.
Solution Approach 2:
The patent introduces a cryptographic intermediary mechanism where the processor acts as a trusted mediator that signs translated addresses. This intermediary layer verifies address integrity without adding complex hardware verification circuits to the integrated MMU, thus maintaining both security and low system complexity.
3Adaptability or versatility
If virtual addresses are used for RDMA to allow dynamic memory allocation, then adaptability is improved, but extra server-side checks are needed for each memory access which increase memory bandwidth consumption, system cost, and power consumption
Solution Approach 1:
The patent performs the address translation and cryptographic signing operation in advance, before the actual RDMA memory access occurs. This preliminary processing allows the signed address to be used directly during the memory operation without requiring additional verification checks, thereby reducing real-time power consumption while maintaining the flexibility of virtual address mapping.
Solution Approach 2:
The patent enables continuous RDMA operations by ensuring the translated address is pre-validated and signed, allowing the memory access to proceed without interruption or additional verification steps. This continuous operation reduces the overhead of repeated checks and lowers overall power consumption while maintaining adaptability.
Data Source
AI summary
An address translation unit for Remote Direct Memory Access (RDMA) of a memory of a processor is provided. The address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address.