Address Translator for Multi-Die Memory Map Compatibility
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Solution Overview
Problem
In system-on-chip designs, the integration of multiple dies within a single package faces challenges such as incompatible memory maps, limited addressable locations, and resource constraints, particularly when transitioning to sub-32 nanometer designs, which can lead to inefficiencies and increased design time due to the dichotomy between low voltage digital logic and higher voltage analog interfaces.
Innovation Solution
A system and method that utilize a first interface to receive memory transactions, an address translator to determine the destination die, and a second interface to forward transactions without modification, allowing for compatible memory mapping and decoupling of digital and analog blocks, enabling modular design and independent validation of dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple dies are integrated within a single package to increase functionality, then the system capability is improved, but the complexity of managing incompatible memory maps and address spaces increases
Solution Approach 1:
The patent introduces an address translator as an intermediary component between dies with different memory maps. This translator receives address translation requests, converts addresses from one memory map format to another, and enables communication between dies that would otherwise be incompatible. The address translator acts as a mediator that resolves the conflict between different address spaces without requiring changes to the individual dies.
Solution Approach 2:
The patent segments the address translation function into a separate, dedicated component (the address translator) rather than embedding it within each die. This segmentation allows the translation logic to be independently managed and configured, reducing the complexity burden on individual dies while enabling multiple dies with different memory maps to coexist in the same package.
2Device complexity
If a unified address space is implemented across multiple dies, then address translation is simplified, but the number of available addressable locations is limited
Solution Approach 1:
The patent changes the parameter of address space organization by allowing each die to maintain its own native address space parameters rather than forcing a unified address space. The address translator dynamically adjusts address parameters (such as address width and mapping relationships) on a per-transaction basis, enabling each die to utilize its full addressable location capacity while still allowing inter-die communication.
3Device complexity
If digital and analog blocks are integrated on the same die, then device count is reduced, but design time increases due to voltage dichotomy constraints
Solution Approach 1:
The patent segments the system into separate digital and analog dies, each optimized for their respective voltage domains. This segmentation allows independent design, validation, and fabrication of digital and analog blocks without the constraints of voltage dichotomy. The address translator and interface components enable these separated blocks to communicate effectively, reducing overall design time while maintaining functional integration.
Solution Approach 2:
The patent introduces interface components and address translators as intermediaries between digital and analog dies with different voltage requirements. These intermediaries handle voltage level translation and signal conditioning, allowing digital and analog blocks to be designed independently at their optimal voltage levels while still communicating seamlessly, thereby reducing design time.
4Ease of manufacture
If dies are fabricated separately with special purpose logic, then manufacturing flexibility is improved, but resource constraints and design coordination become more challenging
Solution Approach 1:
The patent implements a universal address translator design that can handle multiple types of address translation scenarios (different memory maps, different address widths, different mapping schemes) through a single standardized component architecture. This universality simplifies design coordination across multiple separately-fabricated dies, as the same translator methodology can be applied regardless of the specific die configuration or special purpose logic implemented.
Data Source
AI summary
A method may include receiving, at a first integrated circuit die, a memory transaction having an address from a second integrated circuit die. The method may further include determining, at the first integrated circuit die and based on the address, if the transaction is for the first integrated circuit die and, if so, translating the address. If transaction is for a third integrated circuit die, the transaction may be transmitted, without modification to the address, to the third integrated circuit die. The translation may be based upon a first table with each entry including a first address and a second translated address corresponding to the first address, and a second table with each entry including a first address and an indication if the transaction is to be forwarded without modification to the address.