Address Windowing for At-Speed Memory BIST Fail Bitmap Capture
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Solution Overview
Problem
Existing integrated circuit testing methods require large on-chip memory storage to record all memory failures, especially at higher operating frequencies, which is inefficient and costly, and fail to detect speed-sensitive defects effectively.
Innovation Solution
The method involves setting an address window to locate defects in a memory array, comparing output data to expected data, storing failing addresses and bit vectors, and adjusting the window to capture next failing addresses, reducing the need for large on-chip storage and enabling testing at operating frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If large on-chip memory storage is used to record all memory failures, then complete failure information can be captured, but on-chip storage space is consumed and cost increases
Solution Approach 1:
The patent extracts only the essential failure information (failing address and bit vector) from the complete failure data, storing only what is necessary to identify and characterize defects. This extraction principle reduces on-chip storage requirements while maintaining sufficient information for defect analysis.
Solution Approach 2:
The patent uses a compact representation (copy) of failure information by storing only the failing address and a condensed bit vector rather than complete failure data. This copying approach preserves the essential defect characteristics while minimizing storage space consumption.
2Reliability
If memory testing is performed at higher operating frequencies, then speed-sensitive defects can be detected, but existing testing methods cannot effectively detect these defects
Solution Approach 1:
The patent implements dynamic address windowing that adapts to the testing frequency and defect distribution. The address window size and position are adjusted during testing to optimize defect detection at different operating frequencies, enabling effective detection of speed-sensitive defects.
Solution Approach 2:
The patent changes the testing parameters by implementing variable address window sizes and positions based on the operating frequency and observed defect patterns. This parameter adaptation allows the testing method to effectively detect defects across different speed regimes.
3Loss of information
If the entire address space is tested in one pass, then complete coverage is achieved, but large on-chip storage is required to record all failures
Solution Approach 1:
The patent segments the address space into manageable address windows that can be tested and processed in smaller batches. Each window is tested independently, and only the failing addresses within each window are recorded. This segmentation eliminates the need for large on-chip storage while maintaining complete failure coverage across the entire address space.
Solution Approach 2:
The patent uses multiple passes with focused address windows rather than attempting to capture all failures in a single comprehensive pass. This partial action approach tests specific address regions repeatedly, achieving complete coverage through iterative refinement rather than requiring large storage for single-pass recording.
Data Source
AI summary
Integrated circuits with memory built-in self-test (BIST) logic and methods of testing using the same are disclosed. The method includes setting an address window for locating defects in a memory array. The method further includes comparing output data of the memory array to expected data to determine that a defect exists at location “M” in the memory array within the address window. The method further includes storing, in registers, the address M and a resultant bit fail vector associated with the location “M” of the defect found in the memory array. The method further includes resetting the registers to a null value and resetting the address window with a new minimum and maximum address pair, to compare the output data of the memory array to the expected data within the reset address window which excludes address M.