Addressable FIFO Buffer for Non-Destructive Data Access
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Solution Overview
Problem
Existing data management architectures in multi-processor systems, such as FIFO, mailbox, and shared memory, face challenges in efficiently managing data transmission between CPUs on different ASICs, including irreversible read access, memory wastage, and synchronization issues, which limit flexibility and efficiency.
Innovation Solution
An addressable FIFO buffer memory system that allows data words to be stored in chronological order, enabling flexible access and non-destructive reading, with separate invalidation commands to manage memory usage, decoupling clock domains, and avoiding automatic deletion upon read access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional FIFO architecture is used, then data transmission between different clock domains is decoupled, but every read access has an irreversible impact and only the front data element can be accessed
Solution Approach 1:
The patent segments the FIFO buffer into multiple independently addressable memory locations, allowing selective access to individual data elements rather than forcing sequential access from the front. This enables reading any data word at any position without affecting other elements, resolving the contradiction between access flexibility and data integrity.
Solution Approach 2:
The patent introduces an addressable memory interface as an intermediary between the read operation and the FIFO buffer. This intermediary allows random access to any data element while maintaining the underlying FIFO structure, enabling flexible reading without irreversible impact on the buffer contents.
2Adaptability or versatility
If mailbox architecture is used, then random access to all data is enabled, but memory wastage occurs when data sections are of different sizes
Solution Approach 1:
The patent implements dynamic memory allocation within the FIFO buffer, where each data element is assigned a specific address based on its position and size. This dynamic addressing allows efficient packing of variable-sized data sections without wasting memory, while still enabling random access to any element through its address.
3Productivity
If shared memory architecture is used, then simple and fast data management is achieved, but synchronization issues arise when reading and writing occur simultaneously
Solution Approach 1:
The patent segments the shared memory into a FIFO buffer with separate write and read interfaces, each operating independently. The write interface accepts data from the source entity while the read interface serves the destination entity, allowing simultaneous operations without synchronization conflicts.
Solution Approach 2:
The FIFO buffer acts as an intermediary between the write and read operations, decoupling them temporally and spatially. Data is written to the buffer and can be read at any later time without requiring the write operation to complete or synchronize with the read operation.
Data Source
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Figure 2
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AI summary
A device (100) for managing transmission of data words between a data source entity (102) and a data destination entity (104), the device (100) comprising a write interface (106) for receiving data words from the data source entity (102), a read interface (108) for forwarding data words to the data destination entity (104), and a buffer memory (110) adapted for temporarily storing data words to be transmitted from the write interface (106) to the read interface (108), wherein the data words are stored in an order in which they are received from the write interface (106), wherein data words in the buffer memory (110) are addressable for reading at least a part of an addressed data word in such a way that this data word remains stored in the buffer memory (110) after reading.