Addressable JTAG Test Access Port Parallel Device Control
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Solution Overview
Problem
Existing JTAG Test Access Port configurations require multiple TMS signals for parallel device access, leading to increased interface wiring and limitations in applications where signal connections must be minimized, while serial arrangements are less efficient due to dependency on individual device TAP operation rates and fault tolerance.
Innovation Solution
The implementation of an addressable JTAG Test Access Port (ATAP) that allows individual access to parallel devices using an addressing scheme where addresses are transmitted on the falling edge of the TCK signal, enabling access with only the required TDI, TCK, and TMS signals, and incorporating a Device Address Port (DAP) to manage enable signals for Global, Group, and Local access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple TMS signals are used for parallel device access, then individual device access capability is improved, but interface wiring complexity increases
Solution Approach 1:
The patent merges the addressing function into the existing TDI signal path by utilizing the falling edge of TCK for address input. Multiple devices share common TDI, TCK, and TMS signals, while the TAP controller implements intelligent address decoding to selectively access individual devices or groups, eliminating the need for separate TMS lines per device.
Solution Approach 2:
The TAP controller serves as an intermediary that receives address information on the TDI signal and uses it to selectively enable specific devices or groups. This mediator approach allows parallel devices to be accessed individually through a single shared interface without requiring dedicated control lines for each device.
2Device complexity
If serial device arrangement is used, then wiring requirements are reduced, but access efficiency decreases due to dependency on individual device TAP operation rates
Solution Approach 1:
The system dynamically configures device access modes through address-based selection. The TAP controller can adaptively switch between accessing individual devices, groups of devices, or all devices in parallel based on the address provided. This dynamic addressing mechanism allows the system to optimize access efficiency for different operational scenarios while maintaining simplified wiring.
Solution Approach 2:
The addressable TAP interface provides universal access capability that works for both serial and parallel device configurations. The same interface circuitry and signal lines can access devices in series or simultaneously access multiple devices in parallel, making the system versatile and eliminating the trade-off between wiring simplicity and access efficiency.
3Device complexity
If serial device arrangement is used, then wiring is simplified, but fault tolerance decreases
Solution Approach 1:
The addressable TAP interface segments the device access control at the logic level rather than requiring physical segmentation through separate wiring. Each device maintains its unique address, allowing the TAP controller to selectively access individual devices even when multiple devices are connected in parallel. This logical segmentation provides fault isolation while maintaining wiring simplicity.
Data Source
AI summary
The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.