Addressable SPI Bus with Shared Slave Select and CRC Feedback
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Solution Overview
Problem
Existing serial peripheral interface (SPI) bus systems require a dedicated slave select pin for each slave device, leading to increased costs and lack of built-in acknowledgement and error detection mechanisms, resulting in potential data errors and latency issues during data retrieval.
Innovation Solution
An addressable SPI bus system where a single slave select line is used for multiple slaves, with a tri-state output buffer connecting each slave's shift register to a common MISO bus, allowing for address-based data transmission and error detection through CRC verification, reducing latency and eliminating the need for dedicated pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated slave select pin is provided for each slave device, then each slave can be independently selected, but the number of pins required increases leading to higher cost and complexity
Solution Approach 1:
A single slave select line is designed to serve multiple slave devices simultaneously through address decoding logic. Each slave device includes an address register and comparison logic that enables the slave to be identified and selected based on its unique address value, allowing one select line to replace multiple dedicated select lines.
Solution Approach 2:
The slave selection function is segmented into address registration, address comparison, and enable signal generation components within each slave device. This segmentation allows each slave to independently process the common select line and determine whether it should be activated based on its unique address, eliminating the need for dedicated select lines.
2Reliability
If traditional SPI bus is used without built-in acknowledgement, then the system is simpler, but error detection and confirmation mechanisms are lacking leading to potential data errors
Solution Approach 1:
An acknowledgement mechanism is implemented where the selected slave device sends an acknowledgement signal back to the master device after receiving data or commands. This feedback loop allows the master to confirm successful data reception and enables error detection by comparing transmitted and received data, improving communication reliability without requiring completely new hardware.
Solution Approach 2:
The error detection mechanism uses cyclic redundancy check (CRC) calculations performed on a portion of the data (or selective fields) rather than requiring complete data verification. This partial verification approach provides sufficient error detection capability while minimizing the additional processing overhead and protocol complexity.
3Reliability
If wait state is introduced to allow slave to retrieve data from addressable register, then data retrieval reliability improves, but communication latency increases
Solution Approach 1:
The slave device performs data retrieval from its addressable register in advance before the master device needs the data. The slave monitors the slave select line and immediately retrieves the requested data when selected, eliminating the need for the master to introduce wait states. This preliminary action ensures data is ready when needed, reducing communication latency while maintaining reliability.
Solution Approach 2:
The data retrieval timing is made dynamic rather than static. Instead of using fixed wait states that extend latency for all operations, the slave device dynamically retrieves data based on when it is actually selected by the master. This dynamic approach adapts to real-time conditions and eliminates unnecessary delays when data is already available in the slave's buffer.
Data Source
AI summary
An addressable SPI bus and an associated communication protocol. The addressable SPI bus comprises a plurality of slaves each exhibiting a particular address and a shift register whose output is connected to a common MISO bus by a buffer exhibiting a three state output, also known as a tri-state output. The master asserts a single SS line, which is connected in parallel to each of the plurality of slaves, indicating the beginning of a frame, and transmits via the MOSI bus the address of a particular slave of the plurality of slaves, denoted interchangeably the target or destination slave. Responsive to the received address, the target slave enables the three state output associated therewith thus transmitting the output of the target slave shift register to the master via the MISO bus.