Addressable Test Chip with Sensing Circuit for High Density
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Solution Overview
Problem
Existing addressable test chips face challenges with long test periods and low DUT density, which are inadequate for advanced technology nodes, requiring improved test efficiency and higher DUT density to meet manufacturing demands.
Innovation Solution
A test system with an integrated address register and a new type of high-density addressable test chip, incorporating edge-triggered flip-flop registers, counter logic, shifter logic, and a multiplexer, allows for efficient address configuration and sequential or diagnostic testing modes, enabling DUTs to be tested quickly and accurately, with DUT density exceeding 1000/mm2.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional short-ranged test chip is used, then test accuracy is high, but area utilization rate is low
Solution Approach 1:
The patent implements multi-functionality by enabling a single test chip to accommodate multiple DUTs through addressable selection mechanisms. The test chip can dynamically switch between testing different DUTs using control signals, allowing one physical chip to serve multiple testing functions and thereby increasing area utilization rate while maintaining test accuracy for each individual DUT.
2Quantity of substance
If addressable test chip with decoders and switching circuits is used, then DUT number is increased, but peripheral circuit complexity increases
Solution Approach 1:
The patent extracts and simplifies the peripheral circuit by removing unnecessary decoders and complex switching circuits from the traditional addressable test chip architecture. Instead, it uses a simplified control mechanism that directly addresses DUTs through a reduced set of control signals, thereby reducing peripheral circuit complexity while still enabling multiple DUT testing.
Solution Approach 2:
The patent segments the test chip into functional modules where each DUT is independently addressable through specific control signals. This segmentation allows each DUT to be tested independently without requiring complex interconnections between all DUTs, thus reducing overall peripheral circuit complexity while maintaining the ability to test multiple DUTs.
3Quantity of substance
If existing addressable test chip is used, then DUT density is less than 1000/mm2, but advanced technology nodes require higher density
Solution Approach 1:
The patent increases DUT density by utilizing vertical stacking and three-dimensional integration rather than solely expanding horizontally. By arranging DUTs in multiple layers and using vertical interconnects, the test chip achieves higher DUT density (>1000/mm2) without proportionally increasing the test cycle time, as the addressable selection mechanism remains efficient regardless of spatial arrangement.
Data Source
AI summary
An address register includes a plurality of edge-triggered flip-flop registers having an input D, an input R, an input CK, and an output Q; a counter logic; a shifter logic; a multiplexer; input ports including a reset signal RST, a clock signal CLK, a shift enable signal SE, a shift data input signal SI; an output port including address signals ADDR. D is coupled to a data output of the multiplexer; R is coupled to a reset (RST) pad; CK is coupled to a clock (CLK) pad; Q is coupled to an address (ADDR) pad; an input of the counter logic is coupled to ADDR; an input of the shifter logic is coupled to ADDR and the shift data input signal SI; an input of the multiplexer is coupled to SE, an output of the counter logic, and an output of the shifter logic.