Addressable Test Circuit for Transistor Parameter Measurement
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Solution Overview
Problem
The challenge in integrated circuit manufacturing is the instability of process parameters due to small feature sizes, leading to fluctuations in device sizes and performance, which affects yield and reliability, making it difficult to accurately test key transistor parameters.
Innovation Solution
An addressable test circuit with a combination logic circuit, addressing circuit, and switching circuit is used to select and test transistors, allowing for precise measurement of subthreshold leakage current and saturation current using multiple test signal lines, improving area utilization and measurement accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistor feature size is reduced to improve circuit performance, then circuit speed and integration density are improved, but process parameter stability deteriorates and device variability increases
Solution Approach 1:
The test circuit is segmented into multiple independent test channels, each capable of testing transistor parameters independently. This segmentation allows for precise measurement of individual transistor characteristics despite process variability, enabling accurate statistical analysis and modeling of device behavior across different process conditions.
2Device complexity
If conventional test circuits are used without addressable selection, then circuit structure is simple, but test accuracy and area utilization deteriorate
Solution Approach 1:
The test circuit employs addressable selection logic that allows a single test circuit structure to universally test multiple transistors located at different positions in the array. The same test signal lines and measurement circuits can be dynamically configured to test any selected transistor, improving area utilization while maintaining measurement precision through controlled signal routing.
Solution Approach 2:
Address selection logic and switching circuits are introduced as intermediary components between the test signal lines and the transistor array. These intermediaries enable precise control over which transistor is connected to the measurement circuits at any given time, resolving the conflict between circuit simplicity and measurement accuracy by providing controlled signal routing without requiring dedicated test circuits for each transistor.
3Productivity
If multiple transistors are tested simultaneously without addressable selection, then test throughput is high, but measurement accuracy and signal integrity deteriorate due to voltage drops and leakage
Solution Approach 1:
The test circuit employs periodic sequential testing of transistors through addressable selection rather than simultaneous testing. By systematically selecting and testing transistors in a controlled sequence, the circuit maintains signal integrity for each measurement while achieving high overall test throughput through efficient time-multiplexed operation.
Data Source
AI summary
An addressable test circuit is configured to test parameters of a plurality of transistors. The addressable test circuit includes combination logic circuits including a plurality of gate circuits and are configured to select a device under test, a plurality of PADs, a plurality of address bus and data bus; wherein six or more of the data buses are test signal lines. A test method can employ the above address test circuit for testing parameters of a plurality of transistors, where the subthreshold leakage current Ioff and saturation current Idsat are measured in different signal lines respectively to ensure the accurate measurement of the two parameters in one circuit.