Addressable TSV Test Circuit for Defect Localization in 3D ICs
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Solution Overview
Problem
Conventional TSV testing methods in 3D integrated circuits are inefficient and fail to precisely identify abnormal or outlier TSVs, as they measure all TSVs in a chain simultaneously, making it difficult to diagnose individual defects and requiring extensive time and space for testing.
Innovation Solution
A circuit structure with an addressable test array formed by intersecting column and row lines, allowing for selective testing of TSVs, enabling precise identification of defective TSVs and reducing testing time and footprint through a switch circuit that applies test voltage signals and receives current signals from specific rows or columns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional series chaining method is used to test TSVs, then the test circuit footprint area is reduced, but the measurement precision and ability to identify individual defective TSVs deteriorates
Solution Approach 1:
The patent segments the TSV testing into individual addressable units by implementing a memory array structure where each TSV corresponds to a specific memory cell address. This allows individual TSVs to be tested separately rather than in series chains, enabling precise identification of defective TSVs while maintaining compact footprint through the structured array layout.
2Loss of time
If all TSVs are measured simultaneously in one chain, then the testing time is reduced, but the ability to diagnose abnormal TSVs and locate their positions deteriorates
Solution Approach 1:
The patent implements feedback mechanisms through read operations that return resistance values for each addressed TSV. The test controller compares these values against reference ranges and provides feedback to identify abnormal TSVs. This feedback loop enables both rapid screening and detailed diagnosis, resolving the contradiction between speed and diagnostic capability.
3Device complexity
If conventional series chaining method is used, then the device complexity is reduced, but the productivity and testing efficiency deteriorates
Solution Approach 1:
The patent implements a universal test controller that can address and test any TSV in the array through standardized row and column select signals. This multi-functional controller replaces multiple dedicated test circuits, reducing overall device complexity while enabling efficient testing of all TSVs through a single unified interface.
4Measurement precision
If individual TSV testing with addressable array is implemented, then the measurement precision and diagnostic capability are improved, but the test circuit footprint area increases
Solution Approach 1:
The patent nests the TSV test array within the existing memory cell array structure, utilizing the same transistor and capacitor components for dual purposes. The TSV resistance measurement function is nested within the memory cell read operation infrastructure, eliminating the need for separate dedicated test circuitry and preventing footprint area increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for accurate and efficient testing of TSVs, enabling precise diagnosis of defective TSVs and reducing the time and space required for testing, facilitating follow-up electrical and physical failure analysis.
Implementation Method 1
the switch circuit applies test voltage signals through one of the row lines to the TSVs in the same row and receives current signals flowing through the TSVs in the row from the columns lines
Data Source
AI summary
A circuit structure for testing through silicon vias (TSVs) in a 3D IC, including a TSV area with multiple TSVs formed therein, and a switch circuit with multiple column lines and row lines forming an addressable test array, wherein two ends of each TSV are connected respectively with a column line and a row line. The switch circuit applies test voltage signals through one of the row lines to the TSVs in the same row and receives current signals flowing through the TSVs in the row from the columns lines, or the switch circuit applies test voltage signals through one of the column lines to the TSVs in the same column and receives current signals flowing through the TSVs in the column from the row lines.