Addressless Merge Command for Packet Processing
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Solution Overview
Problem
Existing packet processing systems face inefficiencies in merging and storing packet parts across different memory locations, requiring complex address management and processor involvement, which hinders fast packet transmission and processing.
Innovation Solution
The introduction of an addressless merge command and chained CPP bus commands that utilize identifiers and reference values to merge packet parts without explicit addresses, allowing for efficient storage and transmission through dedicated logic circuitry on a Command/Push/Pull bus, enabling packet parts to be stored contiguously in memory without processor intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional address-based merge commands are used, then precise memory location control is achieved, but device complexity and processor involvement increase
Solution Approach 1:
The patent extracts the address management function from the merge command itself and relocates it to a dedicated hardware resource (PPI Allocation Table). The merge command no longer carries addresses but instead references entries in the PPI Allocation Table, which are pre-configured with the necessary address information. This separation simplifies the command structure while maintaining precise memory location control.
Solution Approach 2:
The PPI Allocation Table acts as an intermediary between the merge command and the actual memory operations. It stores pre-computed address information (first address for the item, second address for the merged location) that mediates between the simplified command interface and the complex memory management requirements, eliminating the need for address fields in the command itself.
2Adaptability or versatility
If processor-based instruction execution is used, then flexible control is achieved, but processing time and computational overhead increase
Solution Approach 1:
The patent replaces processor-based instruction execution with dedicated hardware logic circuitry. The merge operation is implemented as a hardware state machine that automatically executes the merge sequence based on the command and PPI Allocation Table entries, eliminating the need for software instructions and processor cycles while maintaining control flexibility.
Solution Approach 2:
The hardware resource performs the merge operation autonomously based on the command parameters and pre-stored address information. The state machine automatically manages the multi-step merge process without requiring processor intervention, reducing processing time while maintaining adaptability through configurable hardware logic.
3Adaptability or versatility
If packet parts are stored in separate memory locations, then storage flexibility is improved, but merging efficiency deteriorates
Solution Approach 1:
The system performs preliminary actions by pre-configuring the PPI Allocation Table with the necessary address information before the merge operation. The first address and second address are prepared in advance in the table entry, allowing the hardware merge logic to execute the merge operation efficiently without requiring dynamic address computation or processor intervention during the actual merge.
4Speed
If dedicated hardware logic is used for merging, then processing speed is improved, but device complexity increases
Solution Approach 1:
The PPI Allocation Table and associated hardware logic serve multiple functions: storing address information, managing memory allocations, and executing merge operations. This multi-functionality reduces the need for separate dedicated hardware components for each function, thereby limiting the increase in device complexity while maintaining high processing speed.
Data Source
AI summary
A chained Command/Push/Pull (CPP) bus command is output by a first device and is sent from a CPP bus master interface across a set of command conductors of a CPP bus to a second device. The chained CPP command includes a reference value. The second device decodes the command, in response determines a plurality of CPP commands, and outputs the plurality of CPP commands onto the CPP bus. The second device detects when the plurality of CPP commands have been completed, and in response returns the reference value back to the CPP bus master interface of the first device via a set of data conductors of the CPP bus. The reference value indicates to the first device that an overall operation of the chained CPP command has been completed.