Semiconductor Package Adhesion Stack With Cutting Surfaces for Reliability

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Solution Overview

Problem

Current semiconductor packages face challenges in enhancing electrical properties and reliability due to limitations in adhesion layer configurations and fabrication methods, which can lead to issues such as exposed adhesion layers and potential cracking.

Innovation Solution

The semiconductor package incorporates a multi-layer adhesion structure with specific cutting surfaces and configurations, including a lower adhesion layer with distinct parts and cutting surfaces, and an upper adhesion layer in contact with these surfaces, surrounded by a molding layer to prevent exposure and enhance reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If adhesion layers are used to connect semiconductor chips, then reliability is improved, but exposed adhesion layers can lead to cracking and reduced durability

Engineering Contradiction:

Improvepackage reliabilityVSAvoidcracking and exposure

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies the molding layer as a protective thin film structure that covers and protects the exposed adhesion layers. The molding layer is formed to extend over the adhesion layers and is planarized to provide a smooth protective surface, preventing cracking and exposure of the underlying adhesion layers while maintaining package reliability.

Inventive Principle:

Principle #30Flexible shells and thin films

Solution Approach 2:

The patent implements protective structures in advance by forming the molding layer that covers the adhesion layers before any potential damage can occur. The planarization process creates a cushioning protective surface that prevents future cracking and exposure, addressing the reliability issue proactively rather than reactively.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If multi-layer adhesion structure is implemented, then electrical properties are improved, but device complexity increases

Engineering Contradiction:

Improveelectrical propertiesVSAvoidadhesion layer configuration

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple adhesion layers (first adhesion layer, second adhesion layer, third adhesion layer) with the molding layer into an integrated protective structure. The molding layer is formed to cover all adhesion layers simultaneously, and the planarization process unifies the surface, reducing the effective complexity while maintaining the electrical benefits of the multi-layer configuration.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20240162193A1Semiconductor package and method of fabricating the same

Publication Date: 2024.05.16 SAMSUNG ELECTRONICS CO LTD

AI summary

Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first semiconductor chip, a lower adhesion layer on the first semiconductor chip, a second semiconductor chip on the lower adhesion layer, an upper adhesion layer on the second semiconductor chip, and a third semiconductor chip on the upper adhesion layer. The lower adhesion layer includes a first cutting surface connected to a top surface of the lower adhesion layer. The upper adhesion layer is in contact with the first cutting surface of the lower adhesion layer.